12-12-2012, 06:23 PM
Digital VLSI Design with Verilog
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Introduction
Course Description
This book may be used as a combined textbook and workbook for a 12-week,
2-day/week interactive course of study. The book is divided into chapters, each
chapter being named for the week and day in the anticipated course schedule.
The course was developed for attendees with a bachelor’s degree in electrical
engineering, or the equivalent, and with digital design experience. In addition to this
kind of background, an attendee was assumed familiar with software programming
in a modern language such as C.
Someone fulfilling the course requirements would expect to spend approximately
12 hours per week for 12 weeks to learn the content and do all the labs. Of course,
now that it is a book, a reader can expect to be able to proceed more at his or
her own pace; therefore, the required preparation can be more flexible than for the
programmed classroom presentation.
Topic List (partial):
Discussion: Modules and hierarchy; Blocking/nonblocking assignment;
Combinational logic; Sequential logic; Behavioral modelling; RTL modelling;
Gate-level modelling; Hardware timing and delays; Verilog parameters;
Basic system tasks; Timing checks; Generate statement; Simulation event
scheduling; Race conditions; Synthesizer operation; Synthesizable constructs;
Netlist optimization; Synthesis control directives; Verilog influence on optimization;
Use of SDF files; Test structures; Error correction basics.
Lab Projects: Shift and scan registers; counters; memory and FIFO models;
digital phase-locked loop (PLL); serial-parallel (and υ-υ) converter;
serializer-deserializer (serdes); primitive gates; switch-level design; netlist
back-annotation.
xix
xx Introduction
Using this Book
The reader is encouraged to read the chapters in order but always to assume that
topics may be covered in a multiple-pass approach: Often, a new idea or language
feature will be mentioned briefly and explained only incompletely; later, perhaps
many pages later, the presentation will return to the idea or feature to fill in details.
Each chapter ends with supplementary readings from two highly recommended
works, textbooks by Thomas and Moorby and by Palnitkar.When a concept remains
difficult, after discussion and even a lab exercise, it is possible that these, or other,
publications listed in the References may help.
Contents of the CD-ROM
The CD-ROM contains problem files and complete solutions to all the lab exercises
in the book. A redundant backup of everything is stored on the CD-ROM in a tar
file, for easy copying to disc in a Linux or Unix working environment.
Be sure to read the ReadMe.txt file on the CD-ROM before using it.
The misc directory on the CD-ROM contains an include file required for Lab 1,
plus some other side files. It contains PDF instructions for basic operation of the
VCS or QuestSim simulators.
The misc directory also contains nonproprietary verilog library files, written
by the author, which allow approximately correct simulation of a verilog netlist.
These netlist models are not correct for design work in TSMC libraries, but they
will permit simulation for training purposes. DO NOT USE THESE VERILOG
LIBRARIES FOR DESIGN WORK. If you are designing for a TSMC tape-out,
use the TSMC libraries provided by Synopsys, with properly back-annotated timing
information.