23-01-2013, 10:50 AM
Distributed (WFQ) Scheduling in Buffered Crossbars
ABSTRACT:
One of the most widely used architectures for packet switches is the crossbar. A
special version of it is the buffered crossbar, where small buffers are associated with the
crosspoints; this simplifies scheduling and improves its efficiency and QoS capabilities to the
point where the switch needs no internal speedup. Furthermore, by supporting variable length
packets throughout a buffered crossbar: (a) there is no need for segmentation and reassembly
(SAR) circuits; (b) no speedup is necessary to support SAR; and © synchronization between the
input and output clock domains is simplified. In turn, the lack of SAR and speedup mean that no
output queues are needed, either. In this paper we present an architecture, a chip layout and cost
analysis, and a performance evaluation of such a 300 Gbps buffered crossbar operating on variable-size packets. The proposed organization is simple yet powerful, can be implemented
using modern technology, and, as the performance results demonstrate, it clearly outperforms
unbuffered crossbars.