26-04-2012, 11:16 AM
Dual Stack Method: A Novel Approach to Low Leakage and Speed Power Product VLSI Design
Dual Stack Method A Novel Approach to Low Leakage and Speed Power Product VLSI Desig.pdf (Size: 784.59 KB / Downloads: 82)
Abstract
The development of digital integrated circuits is
challenged by higher power consumption. The combination of
higher clock speeds, greater functional integration, and smaller
process geometries has contributed to significant growth in
power density. Scaling improves transistor density and
functionality on a chip. Scaling helps to increase speed and
frequency of operation and hence higher performance. As
voltages scale downward with the geometries threshold voltages
must also decrease to gain the performance advantages of the
new technology but leakage current increases exponentially.
Today leakage power has become an increasingly important
issue in processor hardware and software design. In 65 nm and
below technologies, leakage accounts for 30-40% of processor
power. In this paper, we propose a new dual stack approach for
reducing both leakage and dynamic powers. Moreover, the novel
dual stack approach shows the least speed power product when
compared to the existing methods.
Keywords— Dual stack, dual V-th, state saving technique, static
power reduction.
I. INTRODUCTION
Low power has emerged as a principal theme in today’s
electronics industry. The need for low power has caused a
major paradigm shift where power dissipation has become as
important a consideration as performance and area. Two
components determine the power consumption in a CMOS
circuit;
Static power: Includes sub-threshold leakage, drain junction
leakage and gate leakage due to tunneling. Among these, subthreshold
leakage is the most prominent one.
Dynamic power: Includes charging and discharging power
and short circuit power. When technology feature size scales
down, supply voltage and threshold voltage also scale down.
Sub-threshold leakage power increases exponentially as
threshold voltage decreases. Furthermore, the structure of the
short channel device lowers the threshold voltage even lower.
So it is becoming more and more important to reduce leakage
power as well as dynamic power. There are several VLSI
techniques for reducing leakage power [1]–[3]. Each
technique provides an efficient way to reduce leakage power,
but disadvantages of each technique limit its application. In
this paper, we propose a novel dual stack technique that
reduces not only leakage power but also dynamic power. We
summarized and compared the previous techniques with our
new approach.
II. PREVIOUS WORKS
Techniques for leakage power reduction can be grouped
into two categories: state-preserving techniques; where circuit
state is retained and state-destructive techniques; where the
current Boolean output value of the circuit might be lost [4].
A state-preserving technique has an advantage over a state
destructive technique in that with a state-preserving technique
the circuitry can resume operation at a point much later in
time without having to somehow regenerate state [5]. The
most well-known traditional approach is the sleep approach
[1, 4]. In the sleep approach, a "sleep" PMOS transistor is
placed between Vdd and the pull-up network of a circuit and
a "sleep" NMOS transistor is placed between the pull-down
network and Gnd (Fig.1). These sleep transistors turn off the
circuit by cutting off the power rails. The sleep transistors are
turned on when the circuit is active and turned off when the
circuit is idle. By cutting off the power source, this technique
can reduce leakage power effectively. However, output will
be floating after sleep mode, so the technique results in
destruction of state plus a floating output voltage.
Fig. 1. Sleep method
A variation of the sleep approach, the zigzag approach,
reduces wake-up overhead caused by sleep transistors by
placement of alternating sleep transistors assuming a
particular pre-selected input vector [6]. Another technique for
leakage power reduction is the stack approach, which forces a
stack effect by breaking down an existing transistor into two
half size transistors [7]. The divided transistors increase delay
significantly and could limit the usefulness of the approach.
The sleepy stack approach (Fig. 2) combines the sleep and
stack approaches [2, 3]. The sleepy stack technique divides
existing transistors into two half size transistors like the stack
approach. Then sleep transistors are added in parallel to one
of the divided transistors. During sleep mode, sleep
transistors are turned off and stacked transistors suppress
leakage current while saving state. Each sleep transistor,
placed in parallel to the one of the stacked transistors, reduces
resistance of the path, so delay is decreased during active
mode. However, area penalty is a significant matter for this
approach since every transistor is replaced by three transistors
and since additional wires are added for S and S’, which are
sleep signals. Another technique called Dual sleep approach
[8] (Fig. 3) uses the advantage of using the two extra pull-up
and two extra pull-down transistors in sleep mode either in
OFF state or in ON state. Since the dual sleep portion can be
Output
Input
Vdd
S`
S
89
6th International Conference on Electrical and Computer Engineering
ICECE 2010, 18-20 December 2010, Dhaka, Bangladesh
978-1-4244-6279-7/10/$26.00 ©2010 IEEE
made common to all logic circuitry, less number of transistors
is needed to apply a certain logic circuit.
Fig. 2. Sleepy stack
Fig. 3. Dual sleep
III. NOVEL DUAL STACK APPROACH
In this section, the structure and operation of our novel
low-leakage-power design is described. It is also compared
with well-known previous approaches, i.e., the sleepy stack,
dual sleep and sleep transistor methods. First we explain the
circuit operation for a chain of 4 inverters (Fig. 4) in sleep
mode. In sleep mode, the sleep transistors are off, i.e.
transistor N5 and P5 are off. We do so by making S=0 and
hence S’=1. Now we see that the other 4 transistors P6, P7
and N6, N7 connect the main circuit with power rail. Here we
use 2 pmos in the pull-down network and 2 nmos in the pullup
network. The advantage is that nmos degrades the high
logic level while pmos degrades the low logic level. Due to
the body effect, they further decrease the voltage level. So,
the pass transistors decreases the voltage applied across the
main circuit. As we know that static power is proportional to
the voltage applied, with the reduced voltage the power
decreases but we get the advantage of state retention. Another
advantage is got during off mode if we increase the threshold
voltage of N6, N7 and P6, P7. The transistors are held in
reverse body bias. As a result their threshold is high. High
threshold voltage causes low leakage current and hence low
leakage power. If we use minimum size transistors, i.e. aspect
ratio of 1, we again get low leakage power due to low leakage
current. As a result of stacking, P6 and N6 have less drain
voltage. So, the DIBL effect is less for them and they cause
high barrier for leakage current. While in active mode i.e.
S=1 and S’=0, both the sleep transistors (N5 and P5) and the
parallel transistors (N6, N7 and P6, P7) are on. They work as
transmission gate and the power connection is again
established in uncorrupted way. Further they decrease the
dynamic power.
Fig. 4. Dual stack approach (a chain of 4 inverters)
IV. SIMULATION METHODOLOGY
We compare the dual stack approach with Base Case,
Sleep, Sleepy Stack and Dual Sleep techniques. Thus, we
compare four design approaches in terms of power
consumption (dynamic and static), delay and area. To show
that the dual stack approach is applicable to general logic and
memory design, we choose a chain of 4 inverters (Fig. 4) and
a SRAM cell (Fig. 5). We use Avant! Star-HSPICE [9] to
estimate delay and power consumption. Area is estimated
with the help of MICROWIND. The inverter chain uses four
inverters each with W/L=6 for PMOS and W/L=3 for NMOS
for the base case. Sleep transistors in the sleep approach (Fig.
1) are sized such that any sleep transistor between Vdd and a
pull-up network takes the size of the largest transistor in the
pull-up network, and any sleep transistor between Gnd and a
pull-down network takes the size of the largest transistor in
the pull-down network. For example, sleep transistors used in
the pull-up and pull-down networks of the base case inverter
chain have W/L=6 and W/L=3. Transistors in the stack
approach are sized to half of the size of the base case
transistors, e.g., transistors used in pull-up and pull-down of
the base case inverter chain have W/L=3 and W/L=1.5,
respectively. Similarly, transistors, including sleep transistors,
in the sleepy stack approach are sized to half of the size of the
base case transistors. The dual stack transistor size is shown
in Fig. 4. The chosen technologies are BSIM4 PTM Model
[10] and their supply voltages are given in Table-I.
TABLE-I
CHOSEN TECHNOLOGY AND VDD VALUE
180nm 130nm 90nm 65nm 45nm 32nm
1.8V 1.3V 1.2V 1.1V 1.0V 0.9V
S`
S
Output
Input
Vdd
S
S`
Input
Vdd
90
Fig. 5. A SRAM cell in dual stack approach
V. SIMULATION RESULTS
We measure propagation delay, static power consumption,
dynamic power dissipation and area for Base case, Sleep,
Sleepy stack, Dual sleep and Dual stack approaches. Fig.6,
Fig.7, Fig.8 and Fig.9 show the static power consumption, the
propagation delay, the dynamic power dissipation and area
consumed, respectively for a chain of four inverters.