14-02-2013, 10:43 AM
Dynamic Logic Circuits
Dynamic Logic.ppt (Size: 795.5 KB / Downloads: 117)
INTRODUCTION
Dynamic logic is temporary (transient) in that output levels will remain valid only for a certain period of time
Static logic retains its output level as long as power is applied
Dynamic logic is normally done with charging and selectively discharging capacitance (i.e. capacitive circuit nodes)
Precharge clock to charge the capacitance
Evaluate clock to discharge the capacitance depending on condition of logic inputs
Advantages over static logic:
Avoids duplicating logic twice as both N-tree and P-tree, as in standard CMOS
Typically can be used in very high performance applications
Very simple sequential memory circuits; amenable to synchronous logic
High density achievable
Consumes less power (in some cases)
Disadvantages compared to static logic:
Problems with clock synchronization and timing
Design is more difficult
NMOS Dynamic Logic Basic Circuit
The basic dynamic logic gate concept is shown at left (top)
the pass transistor MP is an NMOS device, but could also be implemented with a transmission gate TG
Cx represents the equivalent capacitance of the input gate of the second NMOS device (part of an inverter or logic gate) as well as the PN junction capacitance of MP’s drain (source)
When clock CK goes high, MP is turned on and allows the input voltage Vin to be placed on capacitor Cx
Vin could be a high (“1”) or a low (“0”) voltage
When CK goes low, MP is turned off, trapping the charge on Cx
Operation for a 1 or a 0:
If Vin is high (say VOH), then MP will allow current to flow into Cx, charging it up to Vdd – Vtn (assume CK up level is Vdd)
If Vin is low (say GND), then MP will allow current to flow out of Cx, discharging it to GND
Due to leakage from the drain (source) of MP, Cx can only retain the charge Q for a given period of time (called soft node)
If MP is NMOS, Cx will discharge to GND
If MP is PMOS, Cx will discharge to VDD
If MP is a TG, Cx could discharge in either direction
Leakage and Subthreshold Current in Dynamic Pass Gate
Charge can leak off the storage capacitor Cx mainly from two sources:
PN junction leakage of the NMOS drain (source) junction
Subthreshold current (IOFF) through MP when its gate is down at zero volts
One can solve for the maximum amount of time t that charge can be retained on Cx using the differential equation C dv/dt = I, where
I is the total of the reverse PN junction leakage and the IOFF current
C is the total load capacitance due to gate, junction, wire, and poly capacitance
the maximum allowable V in order to preserve the logic “1” level is known
Typically
The minimum frequency of operation can be found from f ~ 1/
Dynamic Latches with a Single Clock
Dynamic latches eliminate dc feedback leg by storing data on gate capacitance of inverter (or logic gate) and switching charge in or out with a transmission gate
Minimum frequency of operation is typically of the order of 50-100 KHz so as not to lose data due to junction or gate leakage from the node
Can be clocked at high frequency since very little delay in latch elements
Examples:
(a) or (b) show simple transmission gate latch concept
(c ) tri-state inverter dynamic latch holds data on gate when clk is high
(d) and (e) dynamic D register
Cascading Problem in Dynamic CMOS Logic
If several stages of the previous CMOS dynamic logic circuit are cascaded together using the same clock , a problem in evaluation involving a built-in “race condition” will exist
Consider the two stage dynamic logic circuit below:
During pre-charge, both Vout1 and Vout2 are pre-charged to Vdd
When goes high to begin evaluate, all inputs at stage 1 require some finite time to resolve, but during this time charge may erroneously be discharged from Vout2
e.g. assume that eventually the 1st stage NMOS logic tree conducts and fully discharges Vout1, but since all the inputs to the N-tree all not immediately resolved, it takes some time for the N-tree to finally discharge Vout1 to GND.
If, during this time delay, the 2nd stage has the input condition shown with bottom NMOS transistor gate at a logic 1, then Vout2 will start to fall and discharge its load capacitance until Vout1 finally evaluates and turns off the top series NMOS transistor in stage 2
The result is an error in the output of the 2nd stage Vout2