08-08-2012, 03:14 PM
Dynamic Reconfiguration of Distributed Arithmetic Controllers: Design Space Exploration and Trade-off Analysis
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Introduction
Reconfigurable hardware devices like field programmable
gate arrays (FPGA) or coarse grain architectures
are general purpose devices (in the sense, that
they are not manufactured for a specific application) like
micro processors or digital signal processors. In [2] these
architectures are compared using common metrics and the
reconfiguration capability is interpreted to be equivalent to
the programming capability of Von Neumann architectures.
To employ these devices in an efficient way, the implementation
should be specialized to the problem specification in
consideration of the architecture characteristics.
Multicontroller
The task of a controller is to influence the dynamic behaviour
of a system referred as plant. If the input values for
the plant are calculated on basis of the plant’s outputs, we
refer to a control feedback.
In the multiple-model approach the plant, e.g. a complex
mechatronic system in an changing environment, is modeled
as a physical process that is operating in a limited set
of operating regimes. From time to time the plant changes
the operating regime. With conventional methods it might
be possible to design one robust controller that controls the
plant in all operating regimes, but it will not work optimal
for the current operating regime. Parameter adaptive controllers
can be used, but they may respond too slow to abrupt
changes of the plant’s dynamic behavior [5].
Controller module
specification
We assume that every controller module
of fig. 1
is designed as a linear time-invariant system, optimized for
a certain operating regime of the plant. After a time discretization
has been performed the description results in an
equation of form eq. 7.
The input vector of the controller module is represented
by (measurements from sensors of the plant), is the output
vector of the controller (regulating variable to actuators
of the plant) and is the inner state vector of the controller.
The matrices and
are used for the calculation of
the outputs based on the inputs.
Results and conclusion
In this paper we analyzed the FPGA implementation
of applications as a run-time reconfigurable system. We
modeled our example application, a multi-controller, as
task-graph and proposed two different ways how the tasks
share the FPGA resource over time (section 2). Each
task was assumed to have implementations with various
area/execution-time/reconfiguration-time trade-offs. For
the implementation of the tasks (e.g. the controller modules)
an generic distributed arithmetic architecture was
used. We estimated area/execution-time trade-offs and did
numerous synthesis experiments using block-RAM in the
first instance and then distributed-RAM to store the entries
of the distributed arithmetic look-up tables.