03-01-2013, 12:28 PM
ECE428 Xilinx ISE Tutorial
1Tutorial.pdf (Size: 221.1 KB / Downloads: 68)
This tutorial explains the major steps in Xilinx ISE design flow. It consists of three sections. The first section describes
how to enter a design through schematic capture, perform circuit simulation, assign pin locations, implement the design,
and generate FPGA configuration data. Section 2 discuss how to specify timing constraints and perform static timing
analysis. Section 3 explains how to use different design entry methods in a single design project.
Schematic-based FGPA Design flow
Creating a new project
Open Xilinx Project Navigator either from desktop icon or from windows StartMenu. The Project NavigatorWindow
(PNW) is shown in Figure 1. It has four panels. The top panel in the left is the Source Panel that list all the design
components (e.g. schematic, VHDL or Verilog code, and user constraint files) contained in the project. The middle pane
in the left is the Process Panel. From this panel, users can start different design tasks (e.g. synthesize, implement, etc.)
for selected design components. The bottom panel is the Transcript Panel for displaying ISE messages. The right panel
in the Project NavigatorWindow is the Workspace Panel, which serves for difference purposes during the design process.
Creating schematic
From the Project Navigator Window, click Project menu and select New Source. A window as shown in Figure 7
pops up. Select schematic from the left panel and type circuit name mycircuit in the right panel. The directory in which
the schematic will be stored can be also changed in this window. After click Next and close the source summary window.
An ECS window as shown in Figure 8 will pop up. In the left side of the ECS window, there are two overlapped panels,
labeled by Options and Symbols. Click the tab of Symbols to bring the Symbol Panel to the front. The top of the Symbol
Panel is the CategoryWindow that lists all the available component libraries. The second window is the SymbolWindow
displaying component (symbol) names. Below these two windows are two blanks for symbol displaying filter and symbol
orientation selection. The Symbol Information Button is located at the bottom of the Symbol Panel. Clicking this button
will open the corresponding symbol description file which is in PDF format.
Simulating the created design
After drawing the schematic, the next task is to verify the function of the design through logic simulation. The current
ISE tool in the ECE Department is configured to useModelSim for logic simulation. To easily start the simulation process,
a testbench can be created as follows.
From the Project Navigator window, click Project menu and select New Source. Configure the new source window as
shown in Figure 9. In the next window, select mycircuit as shown in Figure 10. After these steps, a testbench summary
window is displayed. Closing the testbench summary window, a timing initialization window as shown in Figure 11 will
appear for specifying setup time, maximum delay as well as clock period and duty cycle (by specifying clock high time
and low time). Thereafter, a waveform window as shown in Figure 12 will be displayed. Use the mouse to toggle input
signal values. Finally, right click the mouse to bring up a pop-up menu and select Set end of testbench. This will set the
time that the simulation will stop. In the waveform window, it is represented by a vertical blue time. The position of the
blue vertical line (also the simulation stop time) can be change with using the mouse. After save the testbench waveform,
testbench file testcir.tbw should be listed in the PNW Source Panel.
Specifying pin locations
There are multiple places in Xilinx ISE design flow that allow users to specify pin locations. In the circuit schematic,
the designer can move cursor to select a input (or output) buffer and right click the mouse to bring up a pop-up menu.
Select Object Properties. The Object PropertyWindow pops up as shown in Figure 14. Click New to bring up the New
PropertyWindow as shown in Figure 15. Enter loc for the Attribute Name and A5 for the Attribute Value.
Design synthesis
In the PNWSource Panel, highlight schematic file mycircuit.sch. In the Process Panel, double click Synthesize-XST to
perform design synthesis. After the synthesis process, green marks appear to indicate the success of the synthesis process.
Yellow marks indicate the existence of warning messages. Red marks indicate the occurrence of errors. Both warning and
error messages will be displayed in the PNW Transcript Panel. Click the ”+” sign in front of Synthesize-XST to see more
options. Double clicking View Synthesis Report will bring up a text window that summarizes the synthesis result, which
includes device usage and timing information. Note that the timing information reported here does not consider effects of
placement and routing parasitics. In addition to synthesis report, the synthesized schematic can also be viewed by double
clicking View RTL Schematic. This is a useful feature when performing static timing analysis as described later.
Design Implementation
The Xilinx ISE implementation process consists of three major steps: Translate, Map, and Placement and Routing
(P&R). According to Xilinx user manual, the difference between Translate and Map is described as follows. ”Translate
consists of a number of various programs that are used to import the design netlist and prepare it for layout. Mapping is
the process of assigning design logic elements to the specific physical elements that actually implement logic functions in
a device.” The mapped physical elements are placed and routed in the final P&R phase. In the ISE tool, users can simply
double click Implement Design to let the tool automatically complete the above three steps. However, advanced features
can be used in the implementation process to have more control over the final outcome.
After the implementation process is complete, double clicking View/Edit Placed Design or View/Edit Routed Design
(Under Place & Route group in the PNW Process Panel) will open new windows to display the placement and routing
results as shown in Figure 18 and 19, respectively. Also, the designer can double click Generate Post-Place & Route
Simulation mode to create HDL netlist for post-layout simulation. After the netlist is generated, highlight testbench file
testcir.tbw in the PNW Source Panel. Double click Simulate Post-Place & Route VerilogModel in the Process Panel to
start simulation. Signals delayed will be observed in the simulation result because interconnect parasitics are considered
in simulation.