18-12-2012, 02:27 PM
EFFICIENT IMPLEMENTATION OF 16-BIT MULTIPLIER-ACCUMULATOR USING RADIX-2 MODIFIED BOOTH ALGORITHM AND SPST ADDER
USING VERILOG
EFFICIENT IMPLEMENTATION.pdf (Size: 679.58 KB / Downloads: 84)
ABSTRACT
In this paper, we propose a new multiplier-and-accumulator (MAC) architecture for low power and high
speed arithmetic. High speed and low power MAC units are required for applications of digital signal
processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc. For improving
the speed and reducing the dynamic power, there is a need to reduce the glitches (1 to 0 transition) and
spikes (0 to 1 transition). Adder designed using spurious power suppression technique (SPST) avoids the
unwanted glitches and spikes, thus minimizing the switching power dissipation and hence the dynamic
power. Radix -2 modified booth algorithm reduces the number of partial products to half by grouping of
bits from the multiplier term, which improves the speed. The proposed radix-2 modified Booth algorithm
MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC.
INTRODUCTION
The important operations in digital signal processing are filtering, convolution, and inner
products. For such operations the required essential elements are multiplier and multiplier-andaccumulator
(MAC). Most digital signal processing methods use non-linear functions such as
discrete cosine transform (DCT) [2] or discrete wavelet transform (DWT) [3]. Basically the
operations consists of repetitive application of multiplication and addition, so the speed and
performance of the operation depends on the speed of the multiplication and addition. For high
speed multiplication, the modified radix-4 Booth’s algorithm (MBA) [4] is commonly used.
However, this cannot completely solve the problem due to long critical path for multiplication
[5], [6].
MODIFIED BOOTH ENCODER
Modified Booth algorithm has been proposed for high speed multiplication .This type of
multiplier operates much faster than an array multiplier for longer operands because its
computation time is proportional to the logarithm of the word length of operands. Booth
multiplication is a technique that allows faster multiplication by grouping the multiplier bits. The
grouping of multiplier bits and Radix-2 Booth encoding reduce the number of partial products to
half. So we take every second column, and multiply by ±1, ±2, or 0, instead of shifting and
adding for every column of the multiplier term and multiplying by 1 or 0.The advantage of this
method is halving of the number of partial products. For Booth encoding the multiplier bits are
formed in blocks of three, such that each block overlaps the previous block by one bit. Start from
the LSB for grouping, and the first block only uses two bits of the multiplier. Figure 6 shows the
grouping of bits from the multiplier term.
Applying SPST to the Modified Booth Encoder
The SPST equipped modified Booth encoder, which is controlled by a detection unit. One of the
two operands as input to the detection unit, which decide whether the Booth encoder calculates
redundant computations. As shown in Figure 10, the latches can, respectively, freeze the inputs of
MUX-4 to MUX-7 or only those of MUX-6 to MUX-7 when PP4 to PP7 or PP6 to PP7 are zero, to
reduce the transition power dissipation.