26-10-2016, 09:12 AM
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Abstract:
In present scenario every process should be rapid, efficient and simple. There are so many algorithms to achieve this.The Implementation of these algorithms requires large number of complex multiplications ,additions etc, so to make multiplication process rapid and simple it’s necessary for a multiplier to be fast and power efficient. To tackle this problem an efficient method of multiplication is used that is generation of partial products is done by using multiplexer and adding reversible logic circuitry which lowers power consumption.Reversible logic gates are very much in demand for the future computing technologies as they are known to produce
zero power dissipation under ideal conditions. This paper proposes an improved design of a multiplier using
reversible logic gates. Multipliers are very essential for the construction of various computational units of a quantum
computer. The quantum cost of a reversible logic circuit can be minimized by reducing the number of reversible
logic gates. In this paper we have designed the multiplier using reversible gates, such as COG gate (acts as MUX), PG gate (acts as Half adder), HNG gate (acts as full adder). We also compared the power reports of multiplier built by irreversible gates and reversible gates.
Introduction
Multiplication is an essential arithmetic operation for common DSP applications such as Filtering, computation of FFTs etc. Modern digital circuits offer a great deal of computation. Conventional combinational logic circuits for these computations are known to dissipate heat for every bit of information that is lost. This is also evident from the second law of thermodynamics which states that any irreversible process leads to loss of energy. R.Landauer [1] showed that any gate that is irreversible necessarily dissipates energy, and each irreversible bit generates k*T ln2 joules of heat where k is Boltzmann’s constant (1.38 x 10-23 joules/Kelvin) and T is temperature in Kelvin. C.H.Bennett [2] in 1973 showed that an irreversible computer can always be made reversible. He also stated that the energy would not be dissipating from the circuit if inputs can be extracted from outputs and it would be possible if and only if reversible gates are used in the circuits. As technology evolves and many more transistors can fit in a given area, the concern for power dissipation as heat arises. According to Moore’s law the numbers of transistors will double every 18 months. Thus energy conservative devices are the prime need at the end of the day. The amount of energy dissipated in a system bears a direct relationship to the number of bits erased during computation A reversible logic gate is an N input, N output logic device with one to one mapping. This helps to determine the outputs from the inputs and also the inputs can be uniquely recovered from the outputs.
Reversible Logic Gates
The important basic reversible logic gate is Feynman gate [8] which is the only 2×2 reversible gate and it is used most popularly by the designers for fan-out purposes. There is also a double Feynman gate [9], Fredkin gate [10] and Toffoli gate [11], New Gate [12], Peres gate [13], all of which can be used to realize important combinational functions and all are 3×3 reversible gates. Some basic reversible gates are shown in Fig. 1.
2.1.1 Feynman Gate: It is 2x2 gate [3]. If the first input i.e. A is given as 1 the second output
will be the complement of the second input i.e. B. so, this gate is also known as Controlled Not
Gate. It can also be used to copy inputs. Quantum cost of this gate is one.
2.1.2 Peres Gate: It is a 3x3 gate [3]. It can be used as a half adder with third input i.e. c as 0.It
also serves the purpose of fan out. Quantum cost of this gate is four.
2.1.3 HNG Gate: It is a 4x4 gate [3]. A single HNG gate can serve as a one bit full adder.
Quantum cost of this gate is six
2.1.4 Fredkin Gate: Fig 4 shows a 3*3 Fredkin gate [4]. The input vector is I (A, B, C) and the output vector is O
(P, Q, R). The output is defined by P=A, Q=A′B?AC and R=A′C?AB. Quantum cost of a Fredkin gate is 5.
CONCLUSION
In this paper, the efficient multiplier built by reversible multiplexer using COG gate is proposed and described. One of the major constraints in reversible logic is to minimize the number of reversible gates used, garbage outputs produced and usage of number of constant inputs. A comparison is made between different parameters with multiplier with irreversible multiplexer and proposed reversible multiplexer COG gates in terms of gate count, garbage output,area,delay and Power. It can be concluded that multiplier with reversible multiplexer COG gate is efficient in different parameters compared to multiplier built using irreversible gates. Thus it can be found that the proposed multiplier is much more efficient with respect to the existing one. Thus for future research, multipliers with more inputs are built for complex multiplications in an algorithm is an interesting area to investigate. Alternate optimization methods are under investigation as a future work.