12-10-2012, 05:51 PM
EIT120 - Introduction to the Structured VLSI Design (Fall 2009)
Arithmetic Logic Unit (ALU) FIR Filter
Arithmetic Logic Unit.pdf (Size: 715.89 KB / Downloads: 26)
Abstract
The work for this lab is divided into two separate and independent parts. Each
part has its own preparation, coding and design flow. The first part is a simple arithmetic
logic unit (ALU); but to be able to provide the inputs and perform the required
operations, a finite state machine (FSM) is also needed. The whole design should
finally be synthesized and downloaded into the FPGA. 7-segment displays on the
FPGA board should be utalized to show the results of the ALU. Therefore, an architecture
in VHDL to drive the 7-segment displays is required. The second part
of this lab is to design a finit impulse response (FIR) filter in VHDL. Furthermore,
a pipelined version of the same filter should also be designed. There is no need to
physically implement them into the FPGA, but a synthesis report is required to compare
the limits of the both designs. In order to pass the lab, preparations and fulfilling
both parts (ALU and FIR) are mandatory.
Lab Preparation
- Go through the entire manual and try to understand the required functionality and
given tasks. Make sure that you have understood what is expected from the lab
before you start coding. If the functionality or any task sounds unclear consult the
lab assistants during the lab session.
- Prepare yourself as much as possible before the lab session.
- Do tasks 1 and 2 of the first part (ALU). Also, task 1 of the second part (FIR) should
be done before the lab session.
- Go through the files that have already been provided in the lab directory. For each
part of this lab, try to figure out how much coding you need to develop to fulfill the
tasks.
Introduction
The purpose of the first part of this lab is to design a simple arithmetic logic unit (ALU).
You do this using VHDL hardware description language. Afterwards, you need to download
the synthesized code to the FPGA board. This is done in order to test and verify
the functionality of the design. The design flow is based on VHDL Modelsim simulator,
XILINX ISE synthesis tools and XILINX Spartan-3 FPGA board for hardware implementation.
The ALU responds to the user’s input commands and performs one of the selected
operation; addition and subtraction. Furthermore, the result needs to be displayed on the
7-segment display module available on the board. In more detail, every input of the ALU
is an 8-bit digit which can be set by an arbitrary selection of the switches on the FPGA
board. The position of every switch represents a binary 0 or 1; therefore, the decimal
range of each of the ALU inputs is an un-signed integer between 0 and 225. The required
functionality of the ALU unit is as follows.
Requirements
- After reset, the value shown on the 7-segment module is simply the decimal representation
of the 8-bit binary value set by the switches on the board.
- When the user has set the first operand (A), a push button on the board (BTN0) can
be used as “enter” to save this value in a register.
- While the first ALU operand has been saved, the second operand (B) can be set by
re-arranging the positions of the switches and should be saved in a separate register
when the “enter” push button is pressed for the second time.
- As soon as the ALU has both its inputs, it can perform the two required operations.
The first operation could be “A+B” as soon as the input B has decided, then by
pressing the button for the third time “A-B” can be performed.
- The ALU output should toggle between “A+B” and “A-B” when the button is
pressed several times.
- The output of the ALU must be continuously shown on the 7-segment display.
Looking at the required functionality it is obvious that a possible implementation
could involve a controller, i.e., a state machine, a datapath containing an ALU, a register
block to keep the ALU input values, a binary to binary-coded-decimal converter
(Bi/BCD) and a driver for the 7-segment display.