04-12-2012, 05:13 PM
VHDL Tutorial
VHDL Tutorial.pdf (Size: 28.72 KB / Downloads: 125)
This tutorial will cover the steps involved in compiling, elaborating and simulating VHDL
design files. The NC-simulator and the ncvhdl compiler under the cadence distribution will be
used for this purpose. This tutorial will cover only the command line option of running all these
tools. A later tutorial will cover the GUI option for the same.
The ncvhdl and nc-simulator binaries live under a different directory structure than the normal
directory structure used by the icfb and other related tools in the cadence distribution. So you will
require a separate .cshrc file to run these tools. The file is available at the class webpage and is
called .cshrc.sim. Copy the file in your home directory and source it whenever you want to run
VHDL simulations. The command for this is source .cshrc.sim. Source the normal .cshrc file
using the command source .cshrc when you want to run any other tools except the nc-simulators
and compilers. You will have to source one of the two files whenever you switch form icfb to
ncvhdl and vice versa.
Next step is to copy some options files and setup a directory structure. It is important that you
follow the steps involved in setting up the directory structure so that your designs are compatible
with the GUI options. Change your directory to cadence using cd cadence. Then make a directory
called vhdl in the cadence directory using mkdir vhdl. Change your working directory to vhdl
using cd vhdl. Now you will have to copy two files into this directory. One is the cds.lib file that
defines the path to some standard vhdl libraries and the hdl.var file that list the options required by
the simulator for proper operation. They are available on the course webpage and a copy is provided
below. Copy these files into your vhdl directory and make sure that they have the following
lines.
Now before we go on to compiling and simulating we need to make a test bench to test the
code that we just entered. A test bench is another VHDL file that uses your design file and gives it
inputs and checks the outputs. The input and output is done using text files through the VHDL
code using inbuilt I/O functions. For making a test bench make are directory called inverter_test
in your ~/cadence/vhdl directory. Then make a vhdl directory under the inverter_test directory the
same way as you did for the inverter. Inside the inverter_test/vhdl directory make a file called
vhdl.vhd and enter the code for you test bench in it. The test bench file is available on the course
webpage and is also shown below. Again the entity should have the same name as the directory
you are designing in. The color forma