06-11-2012, 05:56 PM
Embedded Soft Processor for Sensor Networks
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ABSTRACT
The introduction of smarter and smaller application specific processors has opened doors to the world of intelligent sensor networks. This has led sensors to have their own onboard processing and communication units. These technological advancements have transcended sensors from performing trivial sensing functions to performing more complex operations like monitoring environmental changes, carry out surveillance etc. We are presenting a soft core design that can be easily modified and integrated with other processing units to implement different design features for sensor nodes. The soft core is implemented using Xilinx ISE design tools. The core has been implemented and tested successfully using cycle accurate timing simulation.
1. Introduction
Lately Wireless Sensors have been found to be extremely efficient & cost effective for a variety of applications. This is directly attributable to the advancement in semiconductor technology. Smaller transistor feature size and innovative processor design has made Wireless Sensor Application more viable than ever before. Wireless Sensor Networks have a wide application in the field of distributed sensing. The introduction of sensor nodes has made Wireless Sensor Networks a reality. Nodes in their very basic form consist of a sensor to monitor the environment or physical quantity under investigation, a Microprocessor to process the sensed information, a communication unit to communicate and transfer information to neighboring nodes or base station and an onboard power supply.
Soft Core Processor Architecture
The flexible sensor network node that design in this work included the soft core processor and other interface units that required for supporting different sensor networks applications. Since this work is focusing on the surveillance applications, camera interface and VGA display units will be integrated with the soft core unit to provide the sensor node design (Figure 1).
The soft core processors architecture closely resembles the MIPS processor architecture. The architecture features a 16 -bit data path and executes instructions over multiple clock cycles. The processor operates at a frequency of 50MHz.
The processor functional unit consists of basic sequential and combinational elements (Figure 2). Additional registers are made use to hold data from the previous stage as the instructions are executed over multiple cycles. The data path elements consists of Instruction Register, Data Register, Register File, Program Counter, Exception Program Counter, Arithmetic and logic unit and ALU OUT Register. The Instruction register holds the instruction read from the memory during the fetch clock cycle and provides it to the subsequent stages to complete the instruction execution. The Register File consists of eight 16-bit wide registers. Registers R0 thru R5 are used to hold operands and results during instruction execution, registers R6 and R7 holds the base address for two different memory locations.
Simulation
The VHDL model for the soft core processor architecture was developed using Xilinx ISE design tools. The design was tested for behavior functionality using ModelSim XE III 6.1e simulation software. A Post Route Simulation was also carried out to check the timing correctness of the processor. The cycle-accurate simulation is used for testing every instruction using ModelSim simulator. The design was mapped to Spartan 3A prototyping board for further testing. The board offers state of the art XC3S700A FPGA chip on which the processor soft-core was tested. The FPGA has an internal Block Ram of 360 Kbytes which used to store the program that used for processor testing [3].
Processor Performance
The sensor node processor performance was determined by considering the SPIN protocol as a test bench. The performance was measured in terms of MIPS (Millions of Instructions per Second). An implementation of SPIN protocol using assembly level instructions was used for the purpose (Figure 2).
The performance of the processor in MIPS using the SPIN protocol was computed by considering the clock cycles for each instruction in the program and the number of instructions in the SPIN program. The equation used to compute processor performance in MIPS is given by [2, 4]: