06-12-2012, 06:41 PM
Embedded System Design Modeling, Synthesis, Verification
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Design Verification Methods
• Simulation based methods
• Specify input test vector, output test vector pair
• Run simulation and compare output against expected output
• Semi-formal Methods
• Specify inputs and outputs as symbolic expressions
• Check simulation output against expected expression
• Formal Methods
• Check equivalence of design models or parts of models
• Check specified properties on models
Simulation
• Task : Create test vectors and simulate model
• Inputs
• Specification
– Typically natural language, incomplete and informal
– Used to create interesting stimuli and monitors
• Model of DUT
– Typically written in HDL or C or both
• Output
• Failed test vectors
– Pointed out in different design representations by debugging tools
Improvements to Simulation Environment
• Main drawback is coverage
• Several coverage metrics
– HDL statements, conditional branches, signal toggle, FSM states
• Each metric is incomplete by itself
• Exhaustive simulation for each coverage type is impractical
• Possible Improvements
• Stimulus optimizations
– Language to specify tests concisely vs. exhaustive enumeration
– Write tests for uncovered parts of the model
• Monitor optimizations
– Assertions within design to point to simulation failures
– Better debugging aids (correlation of code, waveforms and netlist)
• Speedup techniques
– Cycle simulation vs. event driven
– Hardware prototyping on FPGA
• Modeling techniques
– Models at higher abstraction level simulate faster
Speedup techniques
• Cycle simulation
• Observe signals once per clock cycle
• Cannot observe glitches within a clock cycle
• Emulation
• Prototype hardware model on FPGAs
• Much faster than software simulation
• In-circuit emulation
– FPGA is inserted on board instead of real component
• Simulation acceleration
– Emulate parts of hardware by interfacing with software simulator
Modeling techniques
• Use higher abstraction for faster simulation
• Untimed functional / Specification model
– Executable specification to check functional correctness
– Simulates at the speed of C program execution but no timing
• Timed architecture model
– Used to evaluate HW/SW partitioning
– Computation distributed onto system components
• Transaction level model
– Used to evaluate system with abstract communication
– Transactions vs. bit toggling (data abstraction)
• Bus functional model
– Communication modeled at pin-accurate / time accurate level
– Computation modeled at functional level
• Cycle accurate model
– HW and SW at cycle accurate level
– Communication at cycle accurate level