30-05-2012, 05:31 PM
Energy Estimation tool design for cache in RISC Machine
Energy Estimation tool design for cache in RISC Machine.doc (Size: 1.06 MB / Downloads: 64)
INTRODUCTION
State of the art microprocessors have one or more levels of on-chip caches. The trend is to increase the cache memory with the increasing transistor budget, because off-chip accesses are at least an order of magnitude slower. By confining memory accesses on-chip, single cycle memory access latency can be achieved using Static RAMs. There is the added advantage of reducing power because driving signals through high capacitance I/O pads is less frequent. An examination of the die photos of high-end microprocessors show that anywhere from 15% to 40% of the die area is dedicated to on-chip caches.
To accurately estimate cache power, first of all we have to develop a model for static RAM cell and identify its main energy dissipating components. We then develop an energy dissipation model for set associative caches based on SRAM cells. We then present architectural improvements to achieve lower energy dissipation without sacrificing access time. The analytical models for estimating cache energy dissipation are then presented based on the energy model for the cache. These require run time statistics of the cache such as hit/miss counts, fraction of read/write requests, number of dirty victims etc. and information about the cache organization such as tag width, line width, and cache capacity etc. to derive the signal transition counts in various cache components.
ENERGY DISSIPATION IN SRAM CELL
In this section we represent the model for energy dissipation in SRAM caches. A SRAM cell is a digital device that consists of four transistor, cross connected in an arrangement that produces a stable logic state an two capacitor are placed in such a way that when is high and is low; in this state, and are off and and are on. In logic state 0, is low but is high; in this state, and are on and and are off. The address line controls two transistor and , in bit line the desired bit value is applied and its complement from in .
LOW POWER CACHE DESIGNS
In every place we have to save energy. So, in architectural design also the energy should be reduced. Here we give some approaches that reduce energy dissipation in cache.
Cache with Data RAM Sub-banking
Since the word offset into the block frame is already available before the cell readout is performed, power savings can be achieved by reading out only the words at the required offset from all the ways. This technique is called sub-banking. Figure 6(b) depicts a 2–way set associative cache with two sub-banks in each data RAM. A sub-bank address decoder is needed to enable only the desired sub-bank before the word line is asserted. The energy efficiency of single level sub-banked cache was also studied in. We extend it to two level cache hierarchies.
CONCLUSION
We presented an analytical model for estimating energy dissipation in cache memory. Here we take some mathematical formulas and try to estimate the energy dissipation in bit lines, word lines, address input lines and output lines. We assumed some capacitance load and take some standard input values corresponding to a cache memory. So, there is possibility of some error calculation in estimation of energy. At the end of this work we gave a idea about low power cache design by two models, one is Block buffering and second one is Cache Sub-banking. Later we will try to implement this low power cache design.