21-05-2012, 03:03 PM
Evaluation of HiCUM for Modeling DC
Evaluation of HiCUM for Modeling DC.ppt (Size: 1.87 MB / Downloads: 23)
Model Extraction Methodology and Technology Details
Transistor Structures used for Parameter Extraction:
(0.32, 0.48, 0.64, 0.96) m x 8.4 m with a CBEBC layout
Scaling by TRADICA and Models extracted on structures with a CBE layout
Simulations and Optimizations done in ADS2001 & ADS2002.
Technology Details:High-Speed and High-Breakdown Versions with ~47GHz and 27 GHz fT and BVCEO of ~3.5V and 5.5V.
Intermodulation Distortion Results
Measurements done using ATN Load-pull system and Simulations
Using Harmonic Balance
2-tone Simulations and Intermodulation Distortion with
50 termination, Sheridan, Murty and others
CMC,April 2001 (PortoRico) & present work
1-tone Simulations and harmonic Distortion with a 50 termination
Schroter et.al., IEEE TED, 47, pp1529-1535 (2000)
2-tone Intermodulation Distortion with matched load and source
Murty et.al., (To be published)
Conclusions
Hicum Model is developed for a SiGe process and good fits
demonstrated for DC, S-parameter and Large-signal characteristics.
The simulations were done in ADS2001/02 and the model
implementation is found to be robust.
(at least at the device level)