14-02-2013, 09:32 AM
SI_UART eVC Manual
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Introduction
This chapter provides a general introduction to eVCs and to SI_UART eVC. It also describes the contents of this manual.
Finally, it gives contact information in case you require further assistance of any sort.
About eVC
An eVC™ is an e Verification Component. It is a ready-to-use, out-of-the-box verification environment, typically
focusing on a specific protocol or architecture (such as Ethernet, AHB, PCI, USB, or UART).
Each eVC comprises a complete set of elements for stimulating, checking, and collecting coverage information
on your device under verification (DUV) implementation of the eVC protocol or architecture. The eVC expedites creation
of a more efficient verification environment for your DUV. An eVC works with both Verilog and VHDL
devices and with all HDL simulators that are supported by the Specman Elite verification tool suite. You can use an
eVC as a full verification environment or add it to an existing environment.
The eVC interface is viewable and hence can be the basis for user extensions. We recommend doing such extensions
in a separate file. Maintaining the eVC in its original form facilitates seamless upgrades.
The eVC implementation is often partially encrypted. An eVC with a partially encrypted implementation
requires a specific feature license (currently obtained only from SiMantis) to enable it.
Module Level Verification
Figure 1 shows the architectural block diagram of a verification environment for verifying a UART device at the
module level. In the UART DUV receive direction, the eVC provides the active transmitter that generates UART
frame traffic. It also collects coverage on the transmitted frames. In the UART DUV transmit direction, the eVC provides
the receiver that collects the traffic sent from the DUV and performs checking and collects coverage on the
incoming traffic.
The eVC also provides a status and configuration interface that is functionally equivalent to the PC16550D
UART device. The configuration settings are used to configure device behavior (i.e. data size, parity type, etc.) and
status settings are updated according to conditions on the eVC transmit, receive, and MODEM lines. Details of this
interface is described in section 4.3.
System Level Verification
During system level verification, UART frame traffic is generated and received by DUV modules. In such cases, it is
required to monitor the UART traffic and also to collect frames to use in system-wide scoreboarding activities. Figure
2 shows this configuration. In this setup, two DUV UART devices communicate through their UART interfaces. In
this case, two SI_UART eVCs are configured as passive receivers for each UART traffic direction where UART traffic
in each direction is monitored and the collected frames are used for the required scoreboarding operations.
Because this eVC is eRM-compliant, it can be easily combined with other eRM-compliant eVCs to construct an
even broader verification environment. For example, you can join SI_UART eVC with the USB eVC at the system
level to verify an UART-USB bridge.
Generating UART Traffic
UART traffic consists of two types of traffic:
• A serial data stream corresponding to a UART data frame
• MODEM Signals
SI_UART eVC provides a physical interface and an application interface. The physical interface is connected to
the DUV and consists of the serial data and MODEM signals. The application interface is used to interact with the
eVC from the verification environment. The application and physical interface of SI_UART eVC are defined based on
the interface for PC16550D UART device. On the application interface side, the register based interface is extended
to create the special conditions required by verification scenarios (i.e. error injection, etc.).
Top-level environment
The top unit that instantiates all other units in SI_UART eVC is the si_uart_env. si_uart_env inherits from any_env.
The si_uart_env, contains the following blocks:
• UART BFM
• Status and Configuration Block
• Monitor
• Coverage for receive and transmit directions
• Transmit sequences to generate data to be transmitted by the eVC
• Physical port interface (to be connected to DUV signals)
• Application interface (to be used by eVC user).
The top level block diagram of SI_UART eVC is shown in figure 5.
The top level SI_UTIL eVC environment members are shown in table 2. This table does not include physical
ports to be connected to the DUV (these ports are discussed in section 4.2). The code fragment below shows an example
of creating an instance of SI_UART eVC. This operation is discussed in more detail in section 6.1.