06-01-2014, 04:33 PM
FAT TREE ENCODER DESIGN FOR ULTRA-HIGH SPEED FLASH A/D CONVERTERS
TREE ENCODER DESIGN.pdf (Size: 108.27 KB / Downloads: 140)
ABSTRACT
The thermometer code-to-binary code encoder has become
the bottleneck of the ultra-high speed flash ADCs. In this
paper, the authors presented the fat tree thermometer code-
to-binary code encoder that is highly suitable for the ultra-
high speed flash ADCs. The simulation and the implemen-
tation results show that the fat tree encoder outperforms the
commonly used ROM encoder in terms of speed and power
for the 6 bit CMOS flash ADC case. The speed is improved
by almost a factor of 2 when using the fat tree encoder,
which in fact demonstrates the fat tree encoder is an effec-
tive solution for the bottleneck problem in ultra-high speed
ADCs.
INTRODUCTION
A flash analog-to-digital converter (ADC) is known for its
high speed operation. An n bit ADC’s front-end consists
of N , 1 (where N = 2n ) voltage comparators, compar-
ing fully parallel the incoming analog signal with N , 1
reference voltages. The comparators produce the digital
thermometer-code (TC), and the remaining back-end of a
flash ADC consists of a thermometer code-to-binary code
encoder, as shown in Figure 1.
FAT TREE ENCODER IMPLEMENTATION
For a more efficient implementation in CMOS, one may re-
place the OR gates with NOR and NAND gates using the
DeMorgan’s theorem, shown in Figure 4. The authors de-
signed the 6 bit fat tree encoder, attempting to make the
layout as much regular as possible.
To evaluate the performance of the fat tree encoder, au-
thors designed ultra-high performance thresholding inverter
ADCs[8] in 0.18m CMOS technology. Figure 5 shows
two complete 6 bit ADC layouts: Figure 5(a) shows the
ADC with fat tree encoder and Figure 5(b) shows the ADC
with ROM encoder.