01-01-2013, 02:23 PM
FAULT TOLERANT NANO-MEMORY WITH FAULT SECURE ENCODER AND DECODER
FAULT TOLERANT NANO-MEMORY.pdf (Size: 622.76 KB / Downloads: 38)
ABSTRACT
Traditionally, memory cells were the only circuitry susceptible to transient faults The supporting
circuitries around the memory were assumed to be fault-free. Due to the increase in soft error rate in logic
circuits, the encoder and decoder circuitry around the memory blocks have become susceptible to soft errors as
well and must be protected. Memory cells have been protected from soft errors for more than a decade; due to
the increase in soft error rate in logic circuits, the encoder and decoder circuitry around the memory blocks have
become susceptible to soft errors as well and must also be protected. In this paper a new approach to design
fault-secure encoder and decoder circuitry for memory designs. The key novel contribution of this paper is
identifying and defining a new class of error-correcting codes whose redundancy makes the design of faultsecure
detectors (FSD) particularly simple. We further quantify the importance of protecting encoder and
decoder circuitry against transient errors, illustrating a scenario where the system failure rate (FIT) is dominated
by the failure rate of the encoder
and decoder. We prove that Euclidean Geometry Low-Density Parity-Check (EG-LDPC) codes have the faultsecure
detector capability.
INTRODUCTION
Memory cells have been protected from soft errors for more than a decade; due to the increase in soft
error rate in logic circuits, the encoder and decoder circuitry around the memory blocks have become
susceptible to soft errors as well and must also be protected. We introduce a new approach to design fault-secure
encoder and decoder circuitry for memory designs.
Nanotechnology provides smaller, faster, and lower energy devices, which allow more powerful and
compact circuitry; however, these benefits come with a cost, the nano scale devices may be less reliable.
Thermal- and shot-noise estimations alone suggest that the transient fault rate of an individual nano scale device
(e.g., transistor or nano wire) may be orders of magnitude higher than today’s devices. As a result, we can
expect combinational logic to be susceptible to transient faults, not just the storage and communication systems.
Therefore, to build fault-tolerant nano scale systems, we must protect both combinational logic and
memory against transient faults. In the present work we introduce a fault-tolerant nano scale memory
architecture which tolerates transient faults both in the storage unit and in the supporting logic (i.e., encoder and
decoder (corrector) circuitry.
Methodology :
In this proposed system, we introduce a fault-tolerant nano scale memory architecture which tolerates transient
faults both in the storage unit and in the supporting logic (i.e., encoder, decoder (corrector), and detector
circuitries).Particularly; we identify a class of Error-Correcting Codes (ECC’s) that guarantees the existence of
a simple fault-tolerant detector design. This class satisfies a new restricted definition for ECC’s which
guarantees that the ECC codeword has an appropriate redundancy structure such that it can detect multiple
errors occurring in both the stored codeword in memory and the surrounding circuitries.
We call this type of Error-Correcting Codes, Fault-Secure Detector capable ECCs (FSD-ECC). The
Parity-check Matrix of an FSD-ECC has a particular structure that the decoder circuit, generated from the
parity-check Matrix, is Fault-Secure.
We use the fault-secure detection unit to design a fault-tolerant encoder and corrector by monitoring
their outputs. If a detector detects an error in either of these units, that unit must repeat the operation to generate
the correct output vector. Using this retry technique, we can correct potential transient errors in the encoder and
corrector outputs and provide a fully fault-tolerant memory system.
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