05-12-2012, 11:53 AM
Removal of Impulse Noise Using Eodt with Pipelined ADC
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Abstract
Corrupted Image and video signals due to impulse noise during the process of signal acquisition and transmission can be corrected. In this paper the effective removal of impulse noise using EODT with pipelined architecture and its VLSI implementation is presented. Proposed technique uses the denoising techniques such as Edge oriented Denoising technique (EODT) which uses 7 stage pipelined ADC for scheduling. This design requires only low computational complexity and two line memory buffers. It’s hardware cost is quite low. Compared with previous VLSI implementations, our design achieves better image quality with less hardware cost. The Verilog code is successfully implemented by using FPGA Spatron-3 family. Index Terms—Image denoising, impulse noise, pipeline architecture, VLSI. 1. Introduction Most of the video and image signals are affected by noise. Noise can be random or white noise with no coherence, or coherent noise introduced by the capturing device's mechanism or processing algorithms. The major type of noise by which most of the signals are corrupted is salt and pepper noise. You might have observed the dark white and black spots in old photos, these kind of noise presented in images are nothing but the pepper and salt noise. Pepper and salt noise together considered as Impulse noise.
Proposed Technique
All previous techniques involve high computational complexity and require large memory which affects the cost and performance of the system. So less memory consumption and reduced computational complexity are become main design aspects. To achieve these requirements Edge Oriented Denoising Technique (EODT) is presented. This requires only two line memory buffers and simple arithmetic operations like addition, subtraction.
Vlsi Implementation Of Eodt
EODT has low computational complexity and requires only two line buffers, so its cost of VLSI implementation is low. For better timing performance, we adopt the pipelined architecture which can produce an output at every clock cycle. In our implementation, the SRAM used to store the image luminance values is generated with the 0.18μm TSMC/Artisan memory compiler. According to the simulation, we found that the access time for SRAM is about 6 ns. Since the operation of SRAM access belongs to the first pipeline stage of our design, we divide the remaining denoising steps into 6 pipeline stages evenly to keep the propagation delay of each pipeline stage around 6 ns.
Extreme data Detector
The extreme data detector detects the minimum and maximum luminance values (MIN in W and MAX in W) in those processed masks from the first one to the current one in the image. If a pixel is corrupted by the fixed value impulse noise, its luminance value will jump to be the minimum or maximum value in gray scale. If (f i,j) is not equal to (MIN in W and MAX in W) , we conclude that (P i,j)is a noise-free pixel and the following steps for de-noising (P i,j) are skipped. If fi,j is equal to MINinW or MAXinW, we set φ=1, check whether its five neighboring pixels are equal to the extreme data and store the binary compared results into B. 3.2 Edge-oriented noise filter To locate the edge existed in the current W, a simple edge catching technique which can be realized easily with VLSI circuit is adopted. To decide the edge, we consider 12 directional differences, from D1toD2, as shown in fig 3. Only those composed of noise free pixels are taken into account to avoid possible misdetection. If a bit in B is equal to 1, it means that the pixel related to the binary flag is suspected to be a noisy pixel. Directions passing through the suspected pixels are discarded to reduce misdetection. In each condition, at most four directions are chosen for low-cost hardware implementation. If there appear over four directions, only four of them are chose according to the variation in angle.
FUTURE WORK
In EODT we are using 12 directional differences and it’s quite difficult to understand and more time consuming. This problem can be solved out by introducing new technology called Reduced EODT. This technique uses only 3 directional differences and only 5 clock cycles are needed to complete the process. But due to only three directional differences the image quality may not be as good as EODT 6.
CONCLUSION
In this paper, an efficient removal of impulse noise using pipelined ADC is presented. The extensive experimental results demonstrate that our design achieves excellent performance in terms of quantitative evaluation and visual quality, even the noise ratio is as high as 90%. For real-time applications, a7-stage pipeline architecture for EODT is developed and implemented. As the outcome demonstrated, EODT outperforms other chips with the lowest hardware cost. The architectures work with monochromatic images, but they can be extended for working with RGB colour images and videos.