21-03-2012, 03:17 PM
FPGA-Based Implementation of RAM with Asymmetric Port Widths for Run-Time Reconfiguration
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INTRODUCTION
In spite of the idea of reconfigurable logic is not novel,
the growing interest on reconfigurable systems in recent
years have been motivated basically by the partial dynamic
reconfiguration capabilities of new Field Programmable Gate
Array (FPGA) devices [1, 2]. The partial dynamic
reconfiguration allows reprogram selected areas of an FPGA
after its initial configuration, while the remainder areas
continue in operation. This solution presents some
disadvantages: the reprogramming cost (e.g. size of
reconfiguration data or reconfiguration latency) is high, the
reconfiguration depends on the placement and routing of the
circuit and the reconfiguration sequences must be generated
as a technology-dependent bitstreams. Moreover, not all
FPGA devices support dynamic reconfiguration.
memories (distributed RAM).
Usually, CAD tools inference RAM memories from HDL
description, but the read and write port widths must be equal
(symmetric RAM). This kind of memory is widely used in
system-on-chip; however, it is not suitable for
memory-based reconfigurable architectures. On the other
hand, CAD tools allow architectural descriptions or provide
GUI facilities to synthesize asymmetric RAMs. The Xilinx
CoreGen tool [5] can be used to implement asymmetric
RAMs using memory blocks. However, distributed RAM
with asymmetric port widths can not be generated.
IMPLEMENTATION OF RAM WITH ASYMMETRIC
WIDTH PORTS
The proposed VHDL architectural description (called
ASYMRAM) and the schematic are shown in Fig. 2 and
Fig. 3, respectively. The ASYMRAM component can be
used as symmetric and asymmetric RAM. The high-level
entity consists of one decoder and a set of basic RAM
components and multiplexors. The multiplexor and the
decoder description use a generic VHDL behaviour
description. The basic RAM component depends on the
specific device. So, it must be described by the designer for
each specific manufacturer using the appropriate primitive or
VHDL behaviour description. This component models a
dual-port RAM with a configurable depth and width. In
order to support ASYMRAM initialization via signal, the
basic RAM component must be designed with this feature.
The RAM specification achieves a high degree of
portability and flexibility by hiding the specific device
architecture. Fig. 4 shows the basic RAM entity (Fig. 4-a)
and different architectures for Xilinx FPGA devices: using 4-
input LUTs (Fig. 4-b), 6-input LUTs available in new
Virtex-5 devices (Fig. 4-c), and SelectRAM blocks (Fig. 4-
d). Each case uses the appropriate available resource.
CONCLUSIONS
This paper presents a VHDL description of asymmetric
RAM. The lack of VHDL templates or library components
to generate asymmetric memories makes difficult its use in
FPGA-based designs. This is especially interesting to
develop memory-based reconfigurable systems.