20-04-2013, 04:10 PM
FPGA Hardware of the LSB Steganography Method
FPGA Hardware.pdf (Size: 675.65 KB / Downloads: 49)
Abstract
Steganography is one of the most powerful techniques
to conceal the existence of hidden secret data inside a cover
object. Images are the most popular cover objects for
steganography, and thus the importance of image steganography.
Embedding secret information inside images requires intensive
computations, and therefore, designing steganography in
hardware speeds up steganography. This work presents a
hardware design of Least Significant Bit (LSB) steganography
technique in a cyclone II FPGA of the Altera family. The design
utilizes the Nios embedded processor as well as specialized logic
to perform the steganography steps. The design balances the
tradeoffs such as imperceptibility, quality and capacity.
INTRODUCTION
Steganography is the art of invisible communication by
concealing information inside other information. The term
steganography is derived from the Greek and literally means
“covered writing” [1]. A steganography system consists of
three elements: cover-object (which hides the secret message),
the secret message and the stego-object (which is the coverobject
with message embedded inside it.) Given the
proliferation of digital images on the internet, and the large
redundant bits present in the digital representation of an image,
images are the most popular cover objects for steganography
[2].
SYSTEM DESCRIPTION
Figure 2. illustrates the main components of the system. It
consists of: steganography unit, Nios processor, SDRAM and
UART interface. The steganography block and Nios processor
are implemented in the FPGA chip Cyclone-II. Both Cyclone-
II and SDRAM are parts of the FPGA board DE2-70.
The steganography block implements LSB steganography
method by concealing the secret information in the CVR using
a combination of 2-bit and 3-bit LSB steganography, referred
to as 2/3-LSB. Each CVR pixel is represented by three bytes.
A single byte of the secret information is concealed in the three
bytes of a CVR pixel as shown in Figure 3.
CONCLUSION
In this paper, we analyzed the performance of different
cases of LSB steganography. We then proposed the 2/3-LSB
design which provides good image quality and facilitate simple
memory access. We also presented the results of test image
executed on the hardware implementation.
Future work should focus on hardware implementation of
more complex random-based LSB mechanisms, as well as
optimizing the design speed and power.