26-09-2016, 01:10 PM
FPGA IMPLEMENTATION OF IMPROVED NINE-LEVEL MULTI-CARRIER AND MULTI-MODULATION-WAVE SPWM
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ABSTRACT
In this method, a novel concept of Multi-levels Multi-Carrier and Multi-Modulation-wave Single Pulse Width Modulation, Multi Carrier Multi Modulation SPWM (MCMM-SPWM- 7,9 levels) strategy is implemented. In the negative half cycle of the MWs, DC offsets related to the amplitude of carrier are set on the three MWs respectively to apply the same comparison logics of the Modulation Waves (MWs) and carrier during positive and negative half cycle of the MWs. Thus, it is implemented with only one Digital Signal Processor (DSP) chip without any other attached logical circuit or controller. The reason for generating the Zero-Crossing Voltage Pulse Disturbance (ZCVPD) in this strategy is analyzed and the elimination of the ZCVPD is proposed. It is verified with the experimental results also. We further analyze the harmonic distortions, area, power, speed and compare them. The method of developing the nine level Multi-Carrier SPWM is introduced. The spectral characters of the conventional multi-modulation-wave based SPWM are originally derived and compared with the previous work by simulation in detail. The theoretical analysis, simulation and experimental results indicate that, the output characters of the proposed strategy are better the conventional one.
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2.INTRODUCTION
Recently, the multilevel inverters become more and more attractive and have obtained expansive foreground not only in the field of the high-voltage and huge-power system but also in the low-voltage and small-power system, such as the photovoltaic generation system, and so on. Various multilevel topologies have been proposed over the recent years. Common ones are cascaded H-bridge, flying capacitor and diode-clamped. Furthermore, the asymmetrical topologies consisted of twokinds of half-bridge legs with different level number arepresented.Compared with the symmetrical topologies, the asymmetrical ones reduce significantly the number of the power switches on the premise of obtaining the same level number of the output voltage. The reduction of the amount of power switches means that the overall loss, cost and the bulk can be further reduced. However, the multilevel PWM strategies, such as the multi-carrier based multilevel SPWM, the selective harmonic elimination PWM, the voltage space vector PWM, etc are difficult to implement only with DSP.
In the multilevel, SPWMs are implemented with the DSP+CPLD or DSP and FPGA platforms. The attached controller increases the cost and decreases the reliability as well. A single-carrier and multi-MW based multilevel SPWM strategy is proposed. However, this kind of SPWM uses the same waveforms in the positive and negative half cycles of the MWs, in the negative half cycle, the compare logics between the MWs and the carrier need to be inversed against the positive ones to implement overall multilevel output PWMwaveforms. If some kind of multilevelPWM strategy suitable for being implemented with DSP is developed, all of the former controlalgorithm and the multilevel PWM strategy can be performed with only one DSP chip, thus the FPGA or the logic circuit is no longerindispensable. ZCVPD in SCMM-SPWM is analyzed and the elimination is proposed. Finally, the spectral characters of the single-carrier and multi-MWs based multi-level SPWM, including the conventional and proposed one, are originally derived and are compared with each other by simulation. The proposed SCMM-SPWM has the following advantages. Thecancellation of the attached logic circuit or controller makes the implementation platform more concise, cheaper and also indirectly improves the reliability. As a result, the competitiveness of the multilevel inverters against the two-level ones applied in the field of the low-voltage and small-power system is further enhanced.
1.3 ELIMINATION OF ZCVPD IN SCMM-SPWM
In Elimination of ZCVPD IN SCMM-SPWM, the reason for generating the ZCVPD is analyzed and the corresponding elimination is proposed. Known as from Figure. 3 that, when the phase angle is close to zero, before 0° angle, V1, V2, V3 and V7 are on and the other switches are off, uout = 0 . If the states of the left arm and the right arm are switched synchronously,namely, after the 0° angle, V1, V2, V3, V7 are turned off and V4, V5, V6, V8 are turned on, uout is still equal to zero. The voltage pulse disturbance will not occur. However, the control signals of the left arm are generated by the PWM generation module in DSP, the control signals of the right arm are generated by the software program.
The essential non-synchronous phenomenon occurs inevitably between the former two control signals. Assuming that the right arm changes its output voltage in advance, namely, V7 are turned off and V8 are turned on first. Before the control signals of the left arm are refreshed, V1, V2, V3 and V8 are on, the output voltage uout= +E. After the control signals of the left arm are refreshed, V4, V5, V6 and V8 are on, the output voltage uout= 0, the output voltage backs to be normal. The action of uout= +E is regarded as thevoltage pulsedisturbance. The duration of uout= +E is equal to the delay time for refreshing the switching states between the left arm and the right arm.
Furthermore, the dead zones between the complementary switch pairs will deteriorate the nonsynchronous phenomenon. Assuming that the inverter drives a resistive-inductive load and the flowing direction of the output current is from B to A (signed in Figure. 5). At 0°, during the exchanging process of the switching state of V7 and V8, the dead zone is set, during the dead time, V7 and V8 are both off. Because the output current holds its direction during the dead zone of V7 and V8, at the same time, V1, V2 and V3 are on, the output current will flows through the anti-parallel diodes of V1, V2, V3 and V8 to the DC source, the output voltage u E out = + also appears as the voltage pulse disturbance. When the duration of the dead zone of V7 and V8 is over, V4, V5, V6 and V8 are on, uout= 0, the voltage pulse disturbance disappears. To the case of 180° angle, the reason is similar to the one of 0° angle; the amplitude of output voltage pulse disturbance is equal to −E. The corresponding solution is proposed anddepicted as follows. Through changing forcibly the switching states of various power switches around the two zero-crossing points, the output voltage can be clamped at someone special level, thus the voltage pulse disturbance can be eliminated.
At 0°, before V7 and V8 are both turned off, setting V3,V4, V5 turn on first. Followed by this operation, all theother power switches are turned off. The corresponding current flowing route is shown in Figure.1.4 (a). In this case, uout = E/3. Then turning V8 on after the delay of dead time, if the output current is not equal to zero at the moment of V8 turning on, the flowing direction of the output current will not change, then the current flowingroute remains unchanged until the current decays to zero. If the output current has been equal to zero, after V8 areturned on, the flowing route of the output current is switched to the case shown in Figure.1.4 (b), in this case,uout = E /3. . The actual three MWs have the same shapes with the waves shown in Figure. 3; the output voltage waveform uout is seven-level. However, the voltage pulse disturbances with the amplitude equal to E arise at the two zero-crossing points, which will increases the harmonics, loss and acoustics noise.
4.4.1 MULTI CARRIER PWM TECHNIQUE
The most common and popular technique of digital pure-sine wave generation is pulse width modulation. The PWM technique involves generation of a digital waveform, for which the dutycycle is modulated such that the average voltage of the waveform corresponds to a pure
sine wave. The simplest way of producing the PWM signal is through comparison of a low-power reference sine wave with a triangle wave. Multicarrier PWM methods uses high switching frequency carrier waves in comparison to the reference waves to generate a sinusoidal output wave.
4.4.2 SIMULATION OF MCMM
Multicarrier PWM technique is simulated as per the circuit shown in the Figureure. In general inverter with m-level, m-1 carrier with same frequency fc and same peak to peak amplitude Ac are disposed. The reference or modulation waveform has peak to peak amplitude Ar and frequency fr. The reference waveform is compared with carrier signals and if it is greater than a carrier signal then switch/device correspond to that carrier is switched on and if the reference is less than carrier signals then device correspond to carrier is switched off. The Sinusoidal pulse width modulation is commonly used in Industrial application. The frequency of reference signal fr determines the inverter output frequency fo and its peak amplitude Ar controls the modulated index M and then in turn the rms output voltage Vo. Here the modulation index is defined as the ratio of amplitude of reference signal to the amplitude of carrier signal
5.RESULTS AND DISCUSSIONS
5.1 XILINX
Xilinx, Inc. (NASDAQ: XLNX) is a supplier of programmable logic devices. It is known for inventing the field programmable gate array (FPGA) and as the first semiconductor company with a fables manufacturing model. Xilinx was founded in 1984 by two semiconductor engineers, Ross Freeman and Bernard Vonderschmitt, who were both working for integrated circuit and solid-state device manufacturer Zilog Corp. Xilinx designs, develops and markets programmable logic products including integrated circuits (ICs), software design tools, predefined system functions delivered as intellectual property (IP) cores, design services, customer training, field engineering and technical support. Xilinx sells both FPGAs and CPLDs programmable logic devices for electronic equipment manufacturers in end markets such as communications, industrial, consumer, automotive and data processing. Xilinx's FPGAs have been used for the ALICE (A Large Ion Collider Experiment) at the CERN European laboratory on the French-Swiss border to map and disentangle the trajectories of thousands of subatomic particles. The Virtex-II Pro, Virtex-4, Virtex-5, and Virtex-6 FPGA families are focused on System-on-Chip (SoC) designers because they include up to two embedded IBM PowerPC cores.
Xilinx FPGAs can run a regular embedded OS (such as Linux or VxWorks) and can implement processor peripherals in programmable logic. Xilinx's IP cores include IP for simple functions (BCD encoders, counters, etc.), for domain specific cores (digital signal processing, FFT and FIR cores) to complex systems (multi-gigabit networking cores, Micro Blaze soft microprocessor, and the compact PIC blaze microcontroller).
Xilinx also creates custom cores for a fee. The ISE Design Suite is the central electronic design automation (EDA) product family sold by Xilinx. The ISE Design Suite features include design entry and synthesis supporting Verilog or VHDL, place-and-route (PAR), completed verification and debug using Chip Scope Pro tools, and creation of the bit files that are used to configureure the chip. Xilinx's Embedded Developer's Kit (EDK) supports the embedded PowerPC 405 and 440 cores (in Virtex-II Pro and some Virtex-4 and -5 chips) and the Micro blaze core. Xilinx's System Generator for DSP implements DSP designs on Xilinx FPGAs.
Xilinx is the only (as of 2007) FPGA vendor to distribute a native Linux freeware synthesis tool chain. The Spartan series targets applications with a low-power footprint, extreme cost sensitivity and high-volume; e.g. displays, set-top boxes, wireless routers and other applications. The Spartan-6 family is built on a 45-nanometer [nm], 9-metal layer, and dual-oxide process technology. The Spartan-6 was marketed in 2009 as a low-cost solution for automotive, wireless communications, flat-panel display and video surveillance applications.
5.2 MODEL SIM
Model Sim eases the process of finding design defects with an intelligently engineered debug environment. The Model Sim debug environment efficiently displays design data for analysis and debug of all languages. Model Sim allows many debug and analysis capabilities to be employed post-simulation on saved results, as well as during live simulation runs. Signal values can be annotated in the source window and viewed in the waveform viewer, easing debug navigation with hyperlinked navigation between objects and its declaration and between visited files.
Race conditions, delta, and event activity can be analyzed in the list and wave windows. User-defined enumeration values can be easily defined for quicker understanding of simulation results. For improved debug productivity, Model Sim also has graphical and textual dataflow capabilities. For example, the coverage viewer analyzes and annotates source code with code coverage results, including FSM state and transition, statement, expression, branch, and toggle coverage.
The VLSI design flow consists of three major domains, namely:
i. Architecture design
ii. HDL design entry
iii. Behavioral simulation
i. Architecture design: This stage involves analysis of the project requirement problem decomposition and functional simulation (if applicable). The output of this stage is a document which describes the future device architecture, structural blocks, their functions and interfaces.
ii. HDL design entry: The device is described in a formal hardware description language (HDL). The most common HDLs are VHDL and Verilog.
iii. Behavioral simulation: The simulator software verifies the functionality and timing of your design or portion of your design. The simulator interprets VHDL or Verilog code into circuit functionality and displays logical results of the described HDL to determine correct circuit operation. Simulation allows you to create and verify complex functions in a relatively small amount of time
5.2.1 FEATURES
i. High-performance, high-capacity engine for the fastest regression.
ii. Native support of Verilog, VHDL, and System C for effective verification of the most sophisticated design environments.
iii. Fast time-to-debug causality tracing
iv. Multi-language debug environment.
v. Advanced code coverage and analysis tools for fast time to coverage closure.
5.3 PWM SIGNAL GENERATION
This architecture is a high speed N-bit free running counter whose output is compared with register output; which stores desired input duty cycle( N-bit value); with the help of comparator. The comparator output is set equal to 1 when both these values are equal. This comparator output is used to set RS latch .The overflow signal from counter is used to reset RS latch. The output of RS latch gives the desired PWM output. This overflow signal is also used to load new Nbit duty cycle in Register. The advantage of these method is that it is used to generate High-frequency PWM output which is not possible in normal counter based approach.
The VHDL code of PWM Generator is then synthesized using Xilinx XST which is a part of Xilinx ISE software. There is an option of Synthesis in process tab of Xilinx ISE which performs the operation of synthesis .The synthesis process is used for optimizing the design architecture selected. The resulting netlist is saved to an NGC file. After design synthesis, synthesis report is generated which gives information about how many logic blocks are used and what is the device utilization of the design architecture synthesized. Synthesis basically maps the behavioral design to gate level design.
Before translating the design, User Constrained file (UCF) is written to assign pin configureuration of the FPGA to the all blocks I/O’s. Once this is done Translate merges together this UCF file and netlist generated after synthesis into Xilinx design file Mapping is done to fit the design into the available resources of target device i.e. FPGA and route them together so that they occupy minimum area and meet timing requirements. This operation produces NCD output file. There is an option of Generate programming file on the process tab of Xilinx ISE which converts the NCD file generated after routing to BIT file. It produces a bit stream for Xilinx Device (FPGA in this case) configureuration. This BIT file will be used to create file to program the FPGA in our future work.
5.4 EXISTING METHOD
• Multi level inverters - low power dissipation, minimized harmonic contents
• Various Topologies - cascaded H-bridge, flying capacitor and diode-clamped
• DSP – Difficult to implement (selective harmonic elimination PWM, the voltage SVPWM)
• In the negative half cycle, it compare logics between the MWs and the carrier need to be inversed against the positive ones to implement overall multilevel output PWM waveforms.
• Seven-level Single-Carrier and Multi-Modulation-wave SPWM (SCMM-SPWM) strategy based on MW reversed during negative-half cycle
• Elimination of Zero-Crossing Voltage Pulse Disturbance (ZCVPD)
• Spectrum Analysis of single-carrier and multi-MWs based multi-level SPWM
• Output characteristics – Identical to Conventional
• Merits : Significant cost reduction and bulk of the implemental platform.