06-12-2012, 11:39 AM
FPGA Implementation of AES Algorithm using Composite Field Arithmetic
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Abstract
A Low area Advanced Encryption Standard
(AES)-128 bit algorithm is proposed in this paper. This
technique is implemented using Composite Field
Arithmetic (CFA) in byte substitution block, inverse byte
substitution block and key expansion block of AES
algorithm. The Composite field arithmetic technique
provides a low area than the Look Up Table (LUT) in SBoxllnverse
S-Box. The proposed technique is presented
with multistage sub-pipe lined architecture in order to
increase the throughput and its performance is compared
with the previous FPGA implementations.
INTRODUCTION
Network Security is important in all aspects of
life. This provides security for the data being
transmitted from one point to another point.
Cryptography is a form of security in which the input
data is converted to encrypted data and is transmitted in
the Encryption module and in the decryption module;
the encrypted data is converted again to decrypted data
which is same as the input data. Several cryptographic
algorithms have been proposed in the past few years.
Some of the cryptographic algorithms are Blow fish,
DES, Triple DES, SAFER, IDEA, RC4, etc.
The Advanced Encryption Standard (AES)
algorithm was selected as the winner algorithm by NIST
[1] (National Institute of Standards and Technology),
which is the federal standard to protect the sensitive
information. AES has already received widespread use
because of its high security, high performance in both
hardware and software implementations.