25-07-2012, 01:37 PM
FinFETs: From Circuit to Architecture
FinFETs From Circuit.ppt (Size: 956 KB / Downloads: 142)
Why Double-gate Transistors ?
DG-FETs can be used to fill this gap
DG-FETs are extensions of CMOS
Manufacturing processes similar to CMOS
Key limitations of CMOS scaling addressed through
Better control of channel from transistor gates
Reduced short-channel effects
Better Ion/Ioff
Improved sub-threshold slope
No discrete dopant fluctuations
FinFET Width Quantization
Electrical width of a FinFET with n fins: W = 2*n*h
Channel width in a FinFET is quantized
Width quantization is a design challenge if fine control of transistor drive strength is needed
E.g., in ensuring stability of memory cells
Motivation: Power Consumption
Traditional view of CMOS power consumption
Active mode: Dynamic power (switching + short circuit + glitching)
Standby mode: Leakage power
Problem: rising active leakage
40% of total active mode power consumption (70nm bulk CMOS) †
Orion-FinFET
Extends ORION for FinFET-based power simulation for interconnection networks
FinFET power libraries for various temperatures and technologies nodes
Power breakdown of interconnection networks for different FinFET modes
Power comparison for different FinFET modes under different traffic patterns
FinFET SRAM and Embedded DRAM Design
FinE: Two-tier FinFET simulation framework for FinFET circuit design space exploration:
Sentaurus TCAD+UFDG SPICE model
Quasi Monte-Carlo simulation for process variation analysis
Thermal analysis using ThermalScope
Yield estimation
Variation-tolerant ultra low-leakage FinFET SRAMs at lower technology nodes
Gated-diode FinFET embedded DRAMs
Extension of CACTI for FinFETs
Selection of any of the FinFET SRAM and embedded DRAM cells
Use of any of the FinFET operating modes
Scaling of FinFET designs from 32nm to 22nm, 16nm and 10nm technology nodes
Accurately modeling the behavior of a wide range of cache configurations.
Conclusions
FinFETs a necessary semiconductor evolution step because of bulk CMOS scaling problems beyond 32nm
Use of the FinFET back gate leads to very interesting design opportunities
Rich diversity of design styles, made possible by independent control of FinFET gates, can be used effectively to reduce total active power consumption
TCMS able to reduce both delay and subthreshold leakage current in a logic circuit simultaneously
Time has arrived to start exploring the architectural trade-offs made possible by switch to FinFETs.