09-11-2012, 01:34 PM
Multilayer or 3D IC technology
3d or multilayer ic.ppt (Size: 3.65 MB / Downloads: 29)
Motivation
Interconnect structures consume more power .
POWER LOSS is main factor.
Speed of switching is less in conventional ic.
Performance Characteristics
Timing
Energy
With shorter interconnects in 3D ICs, both switching energy and cycle time are expected to be reduced
Timing
In current technologies, timing is interconnect driven.
Reducing interconnect length in designs can dramatically reduce RC delays and increase chip performance
The graph below shows the results of a reduction in wire length due to 3D routing.
3D Standard Cell tool Design
3D Cell Placement
Placement by min-cut partitioning
3D Global Routing
Inter-wafer vias
Circuit layout management
MAGIC
3D Standard Cell Placement
Natural to think of a 3D integrated circuit as being partitioned into device layers or planes
Min cut partitioning along the 3rd dimension is same as minimizing vias.
Intro to Global Routing
Overview
Global Routing involves generating a “loose” route for each net.
Assigns a list of routing regions to a net without actually specifying the geometrical layout of the wires.
Followed by detailed routing
Finds the actual geometrical shape of the net within the assigned routing regions.