16-06-2014, 04:26 PM
Flexible Hardware for Fingerprint Image Processing
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Abstract
Reconfigurable computing adds to the traditional
hardware/software design flow a new degree of freedom in the
development of electronic systems. In a system-on-chip
platform, the fact that a MCU makes evolve at run-time a
hardware coprocessor mapped on a FPGA, to execute thus
different compute-intensive tasks in the same silicon-area,
results in a clear earned value applied to the system
implementation: the low-cost reached through the resources
time-multiplexing. Under that approach, this work merges
both reconfigurable computing and HW/SW co-design
technologies to develop an efficient architecture of an
automatic fingerprint authentication system (AFAS) oriented
to real-time embedded application
INTRODUCTION
Nowadays, innovative products like smart cards or
personal data assistants (PDA) make continuous demands on
embedded systems: high performance, high flexibility, low
power consumption and mainly low-cost become more and
more key features for all this kind of applications. Thus,
there exist clear trends towards replacing the typical system
architecture based on a SW-focused microcontroller unit
(MCU) by a HW/SW system-on-chip (SoC) which not only
integrates a processor core, standard peripherals and
embedded memory as the MCU does but also programmable
logic resources. As prices for field programmable gate arrays
(FPGA) come down, these devices are reaching broader
acceptance in the market. That is particularly true in those
compute-intensive fields where high speed signal processing
is required, as image processing applications [1].
FINGERPRINT IMAGE PROCESSING
As procedure, the user sweeps his finger through the
fingerprint sensor surface and a digital fingerprint image is
captured giving rise to an 8-bit gray-scale bitmap of typically
500 dpi resolution. From that moment on, the acquired image
is submitted to a sequence of computationally extensive
stages that finally let send out a verdict about whether that
user fingerprint sample matches the enrolled fingerprint
template to authenticate thus its owner: image segmentation,
normalization, binarization, thinning, features extraction and
matching are the typical computing stages followed by the
AFAS algorithm. In general, in whatever image processing
technique that process a pixel-based input image to generate
an output image, each pixel of the output image gets
dependant not only on the value of the input pixel located
there but also on its neighbors, where the neighborhood
depth is given by the kernel size of the applied filter. Just for
this reason, the 2-D convolution is one of the fundamental
primitives in any digital image processing technique. Its
compute-intensive nature, based on an arithmetic sum of
products, is the key factor for reaching an efficient
implementation of those processors dedicated to enhance or
extract important information contained in the image [3].
Mathematically it is expressed as:
'( , ) 㺌㺌( , ) ( , )
SYSTEM ARCHITECTURE
This work goes in search of an efficient architecture
suitable for embedded automatic fingerprint recognition
systems. For this, a SW-only implementation of the
biometric algorithm is compared with a HW/SW solution
based on reconfigurable HW, in order to highlight the pros
and cons of each option in terms of performance and cost. In
the first approach, all the computing is carried out by a
MCU. In the second one, this same computational load is
partitioned into HW and SW tasks where a FPGA takes
charge of the computation while a MCU controls the
program flow by reconfiguring, at run-time, the HW
coprocessors fitted in the FPGA at each stage of the
biometric algorithm. The architecture is particularly oriented
to embedded applications, as consumer electronic products,
e.g. a PDA with an integrated fingerprint sensor that deploys
the function of authenticating the user. The HW/SW
platform used in this work is constituted by an Altera
EPXA10 SoC [4] and an Atmel FCD4B14 fingerprint sensor
[5]. The Excalibur EPXA10 SoC device combines an
Image Segmentation and Normalization
The acquired fingerprint image is generally split in two
regions: the foreground or region of interest, characterized
by the skin ridges and valleys of sequential clear and dark
tones, and the background or region with no information,
which normally shows a continuous tone. These differences
of tonality present in the gray-scale image let implement the
segmentation algorithm based on the gradient computation.
The gradient operator applied in this work is the Sobel
convolution mask. Concerning size, a kernel 5x5 is
considered to calculate the gradient at each pixel of the input
image. Then, the whole fingerprint image is divided in
blocks of 8x8 pixels and the segmentation criterion is applied
to each one of these unitary blocks: a block is removed or, on
the contrary, it remains in the image depending on its
resultant gradient value compared with a segmentation
threshold. For this, the algorithm computes the directional
gradient terms gY and gX at each pixel and accumulates the
absolute value of both components for the 8x8 pixels of each
block to finally approximate the gradient magnitude as:
Image Noise Suppression
A typical processing stage carried out in an automatic
fingerprint authentication system is to recover the image
information from those areas that have been corrupted by the
noise in the fingerprint acquisition phase. For this, as part of
our enhancement algorithm, we make use of the Dyadic
Scale-Space (DSS) theory. This strategy lets restore the
ridges and valleys of those low quality regions of the
fingerprint image by decomposing it into a series of images
to remove the noise in different scales. Finally, all these
processed images are combined again to reach a more
credible fingerprint image [8]. As result, the normalized
image is convolved with a gaussian filter to obtain a
enhanced image that preserves the valid information
previously lost due to the noise. In our implementation, the
DSS convolution mask is a symmetric kernel 13x13.
Image Field Orientation
The least mean square orientation algorithm is used to
estimate the orientation field of the fingerprint image [7].
The enhanced image coming from the DSS algorithm is now
divided in 8x8 sectors and the gradient is computed again for
each pixel. The local orientation of each block 8x8 is now
computed using the equation:
From a HW point of view, some optimizations have been
done in the algorithm: all the divisions have been converted
into products and shifts, floating-point operands are skipped
and substituted by fixed-point operations, and some
mathematical expressions have been rewritten in order to
optimize its processing. Thus, for instance, the expression
gX
2
-gY
2
can be reworked as (gX+gY)·(gX-gY), since the
synthesis of a multiplier takes much more area than an adder.
Moreover, the HW-SW performance of real-time image
processing applications mainly depends on the data
bandwidth handled. Like this, our platform makes use of a
32-bit AMBA AHB interface to link MCU, FPGA and
SDRAM. The MCU is the AFAS master processor and it
dictates the application flow. Some of the tasks are directly
executed by the MCU and others are carried out in parallel
by the FPGA. The HW tasks covered in this paper are
divided in three different contexts: in a first context a HW
coprocessor takes charge of computing both image
segmentation and normalization, a second context performs
the image DSS-based filtering and a third context fits a
coprocessor that computes the field orientation of the
resultant image. Although each context implements a
dedicated HW coprocessor made to measure of the specific
computing task, all these FPGA-based coprocessors hold a
similar architecture of functional blocks with a defined role,
PERFORMANCE EVALUATION
In a first approach, the image segmentation,
normalization, noise suppression and field orientation
computing processes are carried out only by SW tasks
executed on the MCU running at 50 MHz. The results
concerning time performance are really poor. Next, these
same four phases are synthesized on hardware through three
independent reconfigurable coprocessors that the MCU
sequentially downloads in the FPGA at run-time, following
the sequential execution of the biometric recognition
algorithm. In this second scenario, the FPGA takes charge of
the computing tasks while the MCU is responsible for
handling the application flow by reconfiguring the HW
coprocessors placed in the FPGA at each phase [4]. In this
approach, both MCU and FPGA work at 50 MHz. The
performances comparison is collected in Table I. The results
show that the throughput of the image processing algorithm
notoriously improves when it is executed under specific
hardware instead of under a general-purpose microprocessor.
In the HW-SW approach, in addition to the HW
processing time, the time spent by the MCU to fully
reconfigure the 1 Mgates FPGA and switch from one context
to the next one is 720 ms. This process is carried out through
the configuration controller at 16 MHz. Some details
regarding to the architecture of the image convolver are
gathered in Fig. 2. The convolver dimensions are adjusted in
each context to the filter size required each time. Other
coprocessors are also present to complement every digital
processing stage, as detailed in the table illustrated
CONCLUSIONS AND FUTURE WORK
This work presents an innovative system architecture
applied to an embedded automatic fingerprint recognition
system. A SW-only solution has been compared with a
HW/SW approach based on reconfigurable hardware. The
results prove that a set of reconfigurable HW coprocessors
mapped on a middle-range FPGA lets customize each stage
of the biometric algorithm and reduce the execution time –in
spite of the overhead given by the HW context
reconfiguration– in about two orders of magnitude