21-03-2012, 01:02 PM
8 BIT -Signed multiplication
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INTRODUCTION
Signed multiplication is multiplying two values that are n-bits wide will produce a 2n bit wide result. For example, multiplying -3 (3’b101) by 2 (3’b010) should result in -6 (6’b111010). The multiplier (second factor) is examined bit by bit right to left (least significant to most significant bit) to determine if the multiplicand (first factor) is to be added to the partial result. If so, the multiplicand is aligned so that the least significant bit is under the correct multiplier bit position. If the multiplicand is negative it must be sign extended. However, if the MSB of the multiplier is 1, the multiplicand is actually subtracted. Recall that subtraction is the same as invert and increment.
Verilog provides a very rich set of new signed data types. However, there are issues when performing operations such as sign extension, truncation or rounding, saturation, addition, and multiplication with signed values. These new data types (in theory) free the designer from worrying about some of these signed data type issues. More compact and readable code should result. However, in the spirit of Verilog, usage of this new functionality is “user beware”! Arithmetic manipulation between mixes of signed and unsigned may simulate and synthesize in unintended ways. Assignments between differently sized types may also not result in what the designer intended.
MULTIPLICATION
The two's complement of a binary number is defined as the value obtained by subtracting the number from a large power of two (specifically, from 2N for an N-bit two's complement). The two's complement of the number then behaves like the negative of the original number in most arithmetic, and it can coexist with positive numbers in a natural way.
A two's-complement system or two's-complement arithmetic is a system in which negative numbers are represented by the two's complement of the absolute value; this system is the most common method of representing signed integers on computers. In such a system, a number is negated (converted from positive to negative or vice versa) by computing its two's complement. An N-bit two's-complement numeral system can represent every integer in the range −2N−1 to +2N−1−1. The two's-complement system has the advantage of not requiring that the addition and subtraction circuitry examine the signs of the operands to determine whether to add or subtract. This property makes the system both simpler to implement and capable of easily handling higher precision arithmetic. Also, zero has only a single representation, obviating the subtleties associated with negative zero, which exists in systems. The method of complements can also be applied in base-10 arithmetic, using ten's complements by analogy with two's complements.
INHERENT PARALLELISM
As we move from bit serial towards high radix digit multipliers, the problem of adding the partial products becomes even more complex. Fully propagating all carries up to the most significant bit position in each addition step is not feasible and also not necessary.