25-05-2012, 02:06 PM
Fundamentals of VHDL Programming
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Introduction:
VHDL (Very High Speed IC Hardware description Language) is one of the
standard hardware description language used to design digital systems. VHDL can
be used to design the lowest level (gate level) of a digital system to the highest
level (VLSI module). VHDL though being a rigid language with a standard set of
rules allows the designer to use different methods of design giving different
perspectives to the digital system.
Other than VHDL there are many hardware description languages available in
the market for the digital designers such as Verilog, ABEL, PALASM, CUPL, and etc
but VHDL and Verilog are the most widely used HDLs. The major difference between
hardware description programming languages and others is the integration of time.
Timing specifications are used to incorporate propagation delays present in the
system.
Types of Representation:
VHDL representation can be seen as text file describing a digital system. The
digital system can be represented in different forms such as a behavioral model or a
structural model. Most commonly known as levels of abstraction, these levels help
the designer to develop complex systems efficiently.
Behavioral Model:
Behavioral level describes the system the way it behaves instead of a lower
abstraction of its connections. Behavioral model describes the relationship
between the input and output signals. The description can be a Register
Transfer Level (RTL) or Algorithmic (set of instruction) or simple Boolean
equations.
Register Transfer Level: RTL typically represents data flow within
the systems like data flow between registers. RTL is mostly used for design of
combinational logics.
Algorithmic Level: In this method, specific instruction set of
statements define the sequence of operations in the system. Algorithmic
level is mostly used for design of sequential logics.