14-06-2012, 10:56 AM
Future Directions in Computer Architecture Research
Computer Architecture Research.pdf (Size: 218.21 KB / Downloads: 44)
In the first article, ‘‘The Future of Architectural
Simulation,’’ Doug Burger
and Joel Emer, under the direction of
moderator James Hoe, debate the future
of computer architecture simulation.
They address issues such as simulator
speed and the role of field-programmable
gate arrays, but also tackle some interesting
broader questions. For instance, does
the limited scope of an architectural
simulator lead to incremental research?
And, can we devise shared research
infrastructures that encourage academics
to think long term, on a 10-year horizon?
In the third article, ‘‘Fine-Grained Activation
for Power Reduction in DRAM,’’
Elliott Cooper-Balis and Bruce Jacob
make a clever observation about the
posted-CAS (column-address strobe)
command and synchronous DRAM
power savings. A posted-CAS command
simplifies memory scheduling by being
issued immediately following the
activate command. Since posted-CAS
makes the column addresses available
to the SDRAM before they are needed,
a subset of these addresses can be
used to select a vertical subset (a partial
row) of the selected bank in advance of
column bit selection.
Finally, ‘‘Tuple Pruning Using Bloom
Filters for Packet Classification,’’ by Hyesook
Lim and So Yeon Kim, addresses
the important problem of packet classification
at wire speed in network routers.
Previous approaches, such as tuple
space pruning, require multiple accesses
to off-chip memory. The authors address
this performance bottleneck through the
use of several on-chip Bloom filters that
reduce the number of unnecessary offchip
memory accesses. The approach
is shown to outperform several previous
approaches on multiple metrics.