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GHDL guide
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Introduction
Content of this manual
This manual is the user and reference manual for GHDL. It does not contain an introduction
to VHDL. Thus, the reader should have at least a basic knowledge of VHDL. A good
knowledge of VHDL language reference manual (usually called LRM) is a plus.
What is VHDL?
VHDL is an acronym for Very High Speed Integrated Circuit Hardware Description Lan-
guage which is a programming language used to describe a logic circuit by function, data
flow behaviour, or structure.
VHDL is a programming language: although VHDL was not designed for writing general
purpose programs, you can write any algorithm with the VHDL language. If you are able to
write programs, you will find in VHDL features similar to those found in procedural languages
such as C, Pascal or Ada. VHDL derives most of its syntax and semantics from Ada. Knowing
Ada is an advantage for learning VHDL (it is an advantage in general as well).
However, VHDL was not designed as a general purpose language but as an HDL (hard-
ware description language). As the name implies, VHDL aims at modeling or documenting
electronics systems. Due to the nature of hardware components which are always running,
VHDL is a highly concurrent language, built upon an event-based timing model.
Like a program written in any other language, a VHDL program can be executed. Since
VHDL is used to model designs, the term simulation is often used instead of execution, with
the same meaning.
Like a program written in another hardware description language, a VHDL program can
be transformed with a synthesis tool into a netlist, that is, a detailed gate-level imple-
mentation.
What is GHDL?
GHDL is a shorthand for G Hardware Design Language. Currently, G has no meaning.
GHDL is a VHDL compiler that can execute (nearly) any VHDL program. GHDL is not a
synthesis tool: you cannot create a netlist with GHDL.
Unlike some other simulators, GHDL is a compiler: it directly translates a VHDL file to
machine code, using the GCC back-end and without using an intermediary language such as
C or C++. Therefore, the compiled code should be faster and the analysis time should be
shorter than with a compiler using an intermediary language.
The current version of GHDL does not contain any graphical viewer: you cannot see signal
waves. You can still check with a test bench. The current version can produce a VCD file
which can be viewed with a wave viewer
Starting with a design
Unless you are only studying VHDL, you will work with bigger designs than the ones of the
previous examples.
Let’s see how to analyze and run a bigger design, such as the DLX model suite written by
Peter Ashenden which is distributed under the terms of the GNU General Public License.
Using GRT from Ada
Warning: This topic is only for advanced users knowing how to use Ada and
GNAT. This is provided only for reference, I have tested this once before releasing
GHDL 0.19 but this is not checked at each release.
The simulator kernel of GHDL named GRT is written in Ada95 and contains a very light
and slighly adapted version of VHPI. Since it is an Ada implementation it is called AVHPI.
Although being tough, you may interface to AVHPI.
Reporting bugs
In order to improve GHDL, we welcome bugs report and suggestions for any aspect of
GHDL. Please use the bug tracker on http://gnaprojects/ghdl. You may also
send an email to ghdl[at]free.fr.
If the compiler crashes, this is a bug. Reliable tools never crash.
If your compiled VHDL executable crashes, this may be a bug at run time or the code
produced may be wrong. However, since VHDL has a notion of pointers, an erroneous
VHDL program (using invalid pointers for example) may crash.
If the compiler emits an error message for a perfectly valid input or does not emit an
error message for an invalid input, this may be a bug. Please send the input file and what
you expected. If you know the LRM well enough, please specify the paragraph which has
not been well implemented. If you don’t know the LRM, maybe your bug report will be
rejected simply because there is no bug. In the latter case, it may be difficult to discuss the
issue; and comparisons with other VHDL tools is not a very strong argument.
If a compiler message is not clear enough for you, please tell me. The error messages
can be improved, but I have not enough experience with them.