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ABSTRACT
GSM technology can provide a sophisticated theft alert system for bank locker system. The embedded I/O unit automates the inner door and entry door. The inner door always kept open.
There are two modes in this project one is normal mode and another one is security mode. In normal mode an authorized person can open the locker key and he can close the entry door. At that time GSM never send the message to the required person. If any person tries to open the locker key in security mode, the inner door will be closed automatically and SMS is transferred to the required person’s hand phone. after identifying the theft an authorized person can automate the inner door through the SMS.
The GSM module is connected with the microcontroller through serial port. Using ‘AT’ commands the SMS is transferred to the GSM module. The GSM module converts the digital information into airborne signals. Through GSM network the SMS is transferred to the required person’s hand phone. This system offers better solution for the Bank security system and also it will help you to track the intruder
The embedded microcontroller used here is 89C51 microcontroller. Since, this microcontroller has in-built peripherals it is called as embedded peripheral the microcontroller has flash memory
INTRODUCTION
1.1. OVERVIEW
This Project focuses onto implement GSM ( Global System for Mobile Communication) based Banking Security System. This system is implemented using an embedded microcontroller. The embedded microcontroller used here is 89C51.
Actually, the aim of the project is to implement an Automatic Banking Security System. Security is the protection of something valuable to ensure that it is not stolen, lost, or altered. GSM Based bank safety locker security system provides more reliability and restricts the unauthorized person who is trying to enter into bank. The microcontroller circuitry indicates the theft to the required person and alarm is ON.
Primarily, the system functions with the help of different technologies like the Global Positioning System (GPS), traditional cellular network such as Global System for Mobile Communications (GSM) and other radio frequency medium. Today GSM fitted Banks, cars; ambulances, fleets and police vehicles are common sights on the roads of developed countries. GSM based bank safety locker security system is simple and costs less. When a GSM based bank safety locker security system is installed in a Bank & to enter the unauthorized person means the message will be transferred to a predefined number.
The functional units of our projects are
GSM module
Stepper Motor
LCD Display
Micro Controller 89c51
1.2. STEPPER MOTOR
The type of Stepper motor we used here is Brushless shaft. This helps in smooth rotation. These motors are used to control the Door
1.3. LCD DISPLAY
A liquid crystal display is a thin, flat display device made up of any number of color or monochrome pixels arrayed infront of a light source or reflector. This is used to display the functioning mode of the microcontroller.
1.4.MICRO CONTROLLER 89c51
The device also has four 8-bit I/O ports, three 16-bit timer/event counters, a multi-source, a four-priority-level, nested interrupt structure, an enhanced UART on-chip oscillator and timing circuits. The added features of 89c51 make it a powerful microcontroller for applications that require pulse width modulation, high-speed I/O and up/down counting capabilities such as motor control.
DESCRIPTION
The embedded microcontroller used here is 89C51 microcontroller. Since, this microcontroller has in-built peripherals it is called as embedded controller. The 89C51 microcontroller is a derivative of 8051 microcontroller whose architecture and instructions are same as 8051 microcontroller with some added facilities.
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GSM technology can provide a sophisticated theft alert system for bank locker system. The embedded I/O unit automates the inner door and entry door. The inner door always kept open. There are two modes in this project one is normal mode and another one is security mode. In normal mode an authorized person can open the locker key and he can close the entry door. At that time GSM never send the message to the required person. If any person tries to open the locker key in security mode, the inner door will be closed automatically and SMS is transferred to the required person’s hand phone. after identifying the theft an authorized person can automate the inner door through the SMS.
The GSM module is connected with the microcontroller through serial port. Using ‘AT’ commands the SMS is transferred to the GSM module. The GSM module converts the digital information into airborne signals. Through GSM network the SMS is transferred to the required person’s hand phone. This system offers better solution for the Bank security system and also it will help you to track the intruder.
2.2. GSM MODULE
GSM has been the backbone of the phenomenal success in mobile telecom over the last decade. Now, at the dawn of the era of true broadband services, GSM continues to evolve to meet new demands. GSM is an open, non-proprietary system that is constantly evolving. One of its great strengths is the international roaming capability. This gives consumers seamless and same standardized same number contactability in more than 212 countries. This has been a vital driver in growth, with around 300 million GSM subscribe currently in Europe and Asia. In the Americas, today's 7 million subscribers are set to grow rapidly, with market potential of 500 million in population, due to the introduction of GSM 800, which allows operators using the 800 MHz band to have access to GSM technology too. GSM satellite roaming has extended service access to areas where terrestrial coverage is not available.
GSM differs from first generation wireless systems in that it uses digital technology and time division multiple access transmission methods. Voice is digitally encoded via a unique encoder, which emulates the characteristics of human speech. This method of transmission permits a very efficient data rate/information content ratio.
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Cellular mobile communication is based on the concept of frequency reuse. That is, the limited spectrum allocated to the service is partitioned into, for example, N non-overlapping channel sets, which are then assigned in a regular repeated pattern to a hexagonal cell grid. The hexagon is just a convenient idealization that approximates the shape of a circle (the constant signal level contour from an omni directional antenna placed at the center) but forms a grid with no gaps or overlaps. The choice of N is dependent on many tradeoffs involving the local propagation environment, traffic distribution, and costs. The propagation environment determines the interference received from neighboring co-channel cells, which in turn governs the reuse distance, that is, the distance allowed between co-channel cells (cells using the same set of frequency channels).
The cell size determination is usually based on the local traffic distribution and demand. The more the concentration of traffic demand in the area, the smaller the cell has to be sized in order to avail the frequency set to a smaller number of roaming subscribers and thus limit the call blocking
probability within the cell. On the other hand, the smaller the cell is sized, the more equipment will be needed in the system as each cell requires the necessary transceiver and switching equipment, known as the base station subsystem (BSS), through which the mobile users access the network over radio links. The degree to which the allocated frequency spectrum is reused over the cellular service area, however, determines the spectrum efficiency in cellular systems. That means the smaller the cell size, and the smaller the number of cells in the reuse geometry, the higher will be the spectrum usage efficiency. Since digital modulation systems can operate with a smaller signal to noise (i.e., signal to interference) ratio for the same service quality, they, in one respect, would allow smaller reuse distance and thus provide higher spectrum efficiency. This is one advantage the digital cellular provides over the older analogue cellular radio communication systems. It is worth mentioning that the digital systems have commonly used sectored cells with 120-degree or smaller directional antennas to further lower the effective reuse distance. This allows a smaller number of cells in the reuse pattern and makes a larger fraction of the total frequency spectrum available within each cell. Currently, research is being done on implementing other enhancements such as the use of dynamic channel assignment strategies for raising the spectrum efficiency in certain cases, such as high uneven traffic distribution over cells.
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2.2.1. GSM SPECIFICATION
Device Name : Wavecom
ROM (Flash) : 16Mb
RAM : 2Mb
Operating Voltage : 3.1 – 4.5 V
Receiving Frequency : 925 – 960 MHz
Transmitting Frequency : 880 – 915 MHz
GSM NETWORK
A GSM network is composed of several functional entities, whose functions and interfaces are specified. The GSM network can be divided into three broad parts.
The Mobile Station is carried by the subscriber.
The Base Station Subsystem controls the radio link with the Mobile Station. The Network Subsystem, the main part of which is the Mobile services Switching Center (MSC), performs the switching of calls between the mobile users, and between mobile and fixed network users.
The MSC also handles the mobility management operations. Not shown is the Operations and Maintenance Center, which oversees the proper operation and setup of the network. The Mobile Station and the Base Station Subsystem communicate across the Um interface, also known as the air interface or radio link. The Base Station Subsystem communicates with the Mobile services Switching Center across the A interface.
Mobile Station:
Mobile Equipment (ME) such as hand portable and vehicle mounted unit. Subscriber Identity Module (SIM), which contains the entire customer related information (identification, secret key for authentication, etc.). The SIM is a small smart card, which contains both programming and information. The A3 and A8 algorithms are implemented in the Subscriber Identity Module (SIM). Subscriber information, such as the IMSI (International Mobile Subscribe\
Identity), is stored in the Subscriber Identity Module (SIM). The Subscriber Identity Module (SIM) can be used to store user-defined information such as phonebook entries. One of the advantages of the GSM architecture is that the SIM may be moved from one Mobile Station to another. This makes upgrades very simple for the GSM telephone user. The use of SIM card is mandatory in the GSM world, whereas the SIM (RUIM) is not very popular in the CDMA world.
2.2.2.2. Base Station Subsystem (BSS):
ll radio-related functions are performed in the BSS, which consists of base Station controllers (BSCs) and the base transceiver stations (BTSs).
2.2.2.3. Base Transceiver Station (BTS):
he Base Transceiver Station (BTS) contains the equipment for transmitting and receiving of radio signals (transceivers), antennas, and equipment for encrypting and decrypting communications with the Base Station Controller (BSC). A group of BTSs are controlled by a BSC. Typically a BTS for anything other than a picocell will have several transceivers (TRXs), which allow it to serve several different frequencies and different sectors of the cell (in the case of sectorised base stations). A BTS is controlled by a parent BSC via the Base Station Control Function (BCF). The BCF is implemented as a discrete unit or even incorporated in a TRX in compact base stations. The BCF provides an Operations and Maintenance (O&M) connection to the Network Management System (NMS), and manages operational states of each TRX, as well as software handling and alarm collection.
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2.2.2.4. Base Station Controller (BSC):
The BSC controls multiple BTSs and manages radio channel setup, and handovers. The BSC is the connection between the Mobile Station and Mobile Switching Center. The Base Station Controller (BSC) provides, classicaly, the intelligence behind the BTSs. Typically a BSC has 10s or even 100s of BTSs under its control. The BSC handles allocation of radio channels, receives measurements from the mobile phones, controls handovers from BTS to BTS. A key function of the BSC is to act as a concentrator where many different low capacity connections to BTSs become reduced to a smaller number of connections towards the Mobile Switching Center (MSC) (with a high level of utilisation). Overall, this means that networks are often structured to have many BSCs distributed into regions near their BTSs which are then connected to large centralised MSC sites.
The BSC is undoubtedly the most robust element in the BSS as it is not only a BTS controller but, for some vendors, a full switching center, as well as an SS7 node with connections to the MSC and SGSN. It also provides all the required data to the Operation Support Subsystem (OSS) as well as to the performance measuring centers. A BSC is often based on a distributed computing architecture, with redundancy applied to critical functional units to ensure availability in the event of fault conditions. Redundancy often extends beyond the BSC equipment itself and is commonly used in the power supplies and in the transmission equipment providing the A-ter interface to PCU.
The databases for all the sites, including information such as carrier frequencies, frequency hopping lists, power reduction levels, receiving levels for cell border calculation, are stored in the BSC.
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2.2.2.5. Network Switching Subsystem (NSS):
Network Switching Subsystem is the component of a GSM system that carries out switching functions and manages the communications between mobile phones and the Public Switched Telephone Network. It is owned and deployed by mobile phone operators and allows mobile phones to communicate with each other and telephones in the wider telecommunications network. The architecture closely resembles a telephone exchange, but there are additional functions which are needed because the phones are not fixed in one location. There is also an overlay architecture on the GSM core network to provide packet-switched data services and is known as the GPRS core network. This allows mobile phones to have access to services such as WAP, MMS, and Internet access. All mobile phones manufactured today have both circuit and packet based services, so most operators have a GPRS network in addition to the standard GSM core network.
2.2.2.6. Mobile Switching Centre (MSC):
The Mobile Switching Centre or MSC is a sophisticated telephone exchange, which provides circuit-switched calling, mobility management, and GSM services to the mobile phones roaming within the area that it serves. This means voice, data and fax services, as well as SMS and call divert. In the GSM mobile phone system, in contrast with earlier analogue services, fax and data information is sent directly digitally encoded to the MSC. Only at the MSC is this re-coded into an "analogue" signal. There are various different names for MSCs in different context, which reflects their complex role in the network.
A Gateway MSC is the MSC that determines which visited MSC the subscriber who is being called is currently located. It also interfaces with the Public Switched Telephone Network. All mobile to mobile calls and PSTN to mobile calls are routed through a GMSC. The term is only valid in the context of one call since any MSC may provide both the gateway function and the Visited MSC function, however, some manufacturers design dedicated high capacity MSCs which do not have any BSCs connected to them. These MSCs will then be the Gateway MSC for many of the calls they handle.
The Visited MSC is the MSC where a customer is currently located. The VLR associated with this MSC will have the subscriber's data in it. The Anchor MSC is the MSC from which a handover has been initiated. The Target MSC is the MSC toward which a Handover should take place. An MSC Server is a part of the redesigned MSC concept starting from 3GPP Release 5.
2.2.3. FREQUENCY BAND USAGE:
Since radio spectrum is a limited resource shared by all users, a method must be devised to divide up the bandwidth among as many users as possible. The method chosen by GSM is a combination of Time- and Frequency-Division Multiple Access (TDMA/FDMA). The FDMA part involves the division by frequency of the (maximum) 25 MHz bandwidth into 124 carrier frequencies spaced 200 kHz apart. One or more carrier frequencies are assigned to each base station. Each of these carrier frequencies is then divided in time, using a TDMA scheme. The fundamental unit of time in this TDMA scheme is called a burst period and it lasts 15/26 ms (or approx. 0.577 ms). Eight burst periods are grouped into a TDMA frame (120/26 ms, or approx. 4.615 ms),.
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basic unit for the definition of logical channels. One physical channel is one burst period per TDMA frame.
Channels are defined by the number and position of their corresponding burst periods. All these definitions are cyclic, and the entire pattern repeats approximately every 3 hours. Channels can be divided into dedicated channels, which are allocated to a mobile station, and common channels, which are used by mobile stations in idle mode. A traffic channel (TCH) is used to carry speech and data traffic. Traffic channels are defined using a 26-frame multiframe, or group of 26 TDMA frames. The length of a 26-frame multiframe is 120 ms, which is how the length of a burst period is defined (120 ms divided by 26 frames divided by 8 burst periods per frame). Out of the 26 frames, 24 are used for traffic, 1 is used for the Slow Associated Control Channel (SACCH) and 1 is currently unused. TCHs for the uplink and downlink are separated in time by 3 burst periods, so that the mobile station does not have to transmit and receive simultaneously, thus simplifying the electronics. In addition to these full-rate TCHs, there are also half-rate TCHs defined, although they are not yet implemented. Half-rate TCHs will effectively double the capacity of a system once half-rate speech coders are specified (i.e., speech coding at around 7 kbps, instead of 13 kbps). Eighth-rate TCHs are also specified, and are used for signalling.
WORKING
The GSM module is connected with the controller. As the controller is keep on monitoring the doors and locker key, when the door get opened, the microcontroller sends the command “AT” to initiate the module. Now the module sends an sms as “Theft Occurred” to the already fed mobile number. Thus the information is passed from the module to the Authorized person. Whenever it receives the correct password from the mobile, it will inform the microcontroller to open the door.
2.2.5. FEATURES
Performance - Fast with high real throughput
Integrity - Secure controlled data transfer
Network Access - Quick and consistent
Contention Control - Avoid conflicts and collisions
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Installation - Simple quick installation
Frequency Choice - Choice of RF bands to suit different terrains
Network Diagnostics - For ease of maintenance and cost saving
2.3. STEPPER MOTOR
A stepper motor is a brushless, synchronous electric motor that can divide a full rotation into a large number of steps, for example, 200 steps. Thus the motor can be turned to a precise angle.
Character generator ROM
Now you might be thinking that when you send an ascii value to DDRAM, how the character is displayed on LCD? so the answer is CGROM. The character generator ROM generates 5 x 8 dot or 5 x 10 dot character patterns from 8-bit character codes. It can generate 208 5 x 8 dot character patterns and 32 5 x 10 dot character patterns. User defined character patterns are also available by mask-programmed ROM.
Busy flag
Busy Flag is an status indicator flag for LCD. When we send a command or data to the LCD for processing, this flag is set (i.e BF =1) and as soon as the instruction is executed successfully this flag is cleared (BF = 0). This is helpful in producing and exact amount of delay for the LCD processing. To read Busy Flag, the condition RS = 0 and R/W = 1 must be met and The MSB of the LCD data bus (D7) act as busy flag. When BF = 1 means LCD is busy and will not accept next command or data and BF = 0 means LCD is ready for the next command or data to process.
Instruction register (IR) and data register (DR)
There are two 8-bit registers in HD44780 controller Instruction and Data register. Instruction register corresponds to the register where you send commands to LCD e.g LCD shift command, LCD clear, LCD address etc. and Data register is used for storing data which is to be displayed on LCD. When send the enable signal of the LCD is asserted, the data on the pins is latched in to the data register and data is then moved automatically to the DDRAM and hence is displayed on the LCD.
Data Register is not only used for sending data to DDRAM but also for CGRAM, the address where you want to send the data, is decided by the instruction you send to LCD.
16 x 2 Alphanumeric LCD Module Features
• Intelligent, with built-in Hitachi HD44780 compatible LCD controller and RAM providing simple interfacing
• 61 x 15.8 mm viewing area
• 5 x 7 dot matrix format for 2.96 x 5.56 mm characters, plus cursor line
• Can display 224 different symbols
• Low power consumption (1 mA typical)
• Powerful command set and user-produced characters
• TTL and CMOS compatible
• Connector for standard 0.1-pitch pin headers
A BRIEF HISTORY OF 8051
In 1981, Intel Corporation introduced an 8 bit microcontroller called 8051. This microcontroller had 128 bytes of RAM, 4K bytes of chip ROM, two timers, one serial port, and four ports all on a single chip. At the time it was also referred as “A SYSTEM ON A CHIP”
AT89S52:
The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller, which provides a highly flexible and cost-effective solution to many, embedded control applications. The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic
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for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM con-tents but freezes the oscillator, disabling all other chip functions until the next interrupt
NECESSITY OF MICROCONTROLLERS:
Microprocessors brought the concept of programmable devices and made many applications of intelligent equipment. Most applications, which do not need large amount of data and program memory, tended to be costly.
The microprocessor system had to satisfy the data and program requirements so, sufficient RAM and ROM are used to satisfy most applications .The peripheral control equipment also had to be satisfied.
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Therefore, almost all-peripheral chips were used in the design. Because of these additional peripherals cost will be comparatively high.
An example:
8085 chip needs:
An Address latch for separating address from multiplex address and data.32-KB RAM and 32-KB ROM to be able to satisfy most applications. As also Timer / Counter, Parallel programmable port, Serial port, and Interrupt controller are needed for its efficient applications.
In comparison a typical Micro controller 8051 chip has all that the 8051 board has except a reduced memory as follows.
4K bytes of ROM as compared to 32-KB, 128 Bytes of RAM as compared to 32-KB.
Bulky:
On comparing a board full of chips (Microprocessors) with one chip with all components in it (Microcontroller).
Debugging:
Lots of Microprocessor circuitry and program to debug. In Micro controller there is no Microprocessor circuitry to debug.
Slower Development time: As we have observed Microprocessors need a lot of debugging at board level and at program level, where as, Micro controller do not have the excessive circuitry and the built-in peripheral chips are easier to program for operation.
So peripheral devices like Timer/Counter, Parallel programmable port, Serial Communication Port, Interrupt controller and so on, which were most often used were integrated with the Microprocessor to present the Micro controller .RAM and ROM also were integrated in the same chip. The ROM size was anything from 256 bytes to 32Kb or more. RAM was optimized to minimum of 64 bytes to 256 bytes or more.
Microprocessor has following instructions to perform:
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1. Reading instructions or data from program memory ROM.
2. Interpreting the instruction and executing it.
3. Microprocessor Program is a collection of instructions stored in a Nonvolatile memory.
4. Read Data from I/O device
5. Process the input read, as per the instructions read in program memory.
6. Read or write data to Data memory.
7. Write data to I/O device and output the result of processing to O/P device.
Introduction to AT89S52
The system requirements and control specifications clearly rule out the use of 16, 32 or 64 bit micro controllers or microprocessors. Systems using these may be earlier to implement due to large number of internal features. They are also faster and more reliable but, the above application is satisfactorily served by 8-bit micro controller. Using an inexpensive 8-bit Microcontroller will doom the 32-bit product failure in any competitive market place. Coming to the question of why to use 89S52 of all the 8-bit Microcontroller available in the market the main answer would be because it has 8kB Flash and 256 bytes of data RAM32 I/O lines, three 16-bit timer/counters, a Eight-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry.
In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next hardware reset. The Flash program memory supports both parallel programming and in Serial In-System Programming
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By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.
FEATURES
Compatible with MCS-51 Products
8K Bytes of In-System Reprogrammable Flash Memory
Fully Static Operation: 0 Hz to 33 MHz
Three-level Program Memory Lock
256 x 8-bit Internal RAM
32 Programmable I/O Lines
Three 16-bit Timer/Counters
Eight Interrupt Sources
Programmable Serial Channel
Low-power Idle and Power-down Modes
4.0V to 5.5V Operating Range
Full Duplex UART Serial Channel
Interrupt Recovery from Power-down Mode
Watchdog Timer
Dual Data Pointer
Power-off Flag
Fast Programming Time
Flexible ISP Programming (Byte and Page Mode)
PIN DESCRIPTION
Pin Description
VCC
Supply voltage.
GND
Ground.
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 can also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification.
External pullups are required during program verification.
Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table. Port 1 also receives the low-order address bytes during Flash programming and verification.
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also serves the functions of various special features of the AT89S52, as shown in the following table. Port 3 also receives some control signals for Flash programming and verification.
RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 96 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled. ALE/PROG Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
PSEN
Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.
EA/VPP
External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage
(VPP) during Flash programming.
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.