25-08-2017, 09:32 PM
HARDWARE DESCRIPTIVE LANGUAGE (HDL)
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Brief History:
• VHDL Was developed in the early 1980s for managing design problems that involved large circuits and multiple teams of engineers.
• Funded by U.S. Department of Defense.
• The first publicly available version was released in 1985.
• In 1986 IEEE (Institute of Electrical and Electronics Engineers, Inc.) was presented with a proposal to standardize the VHDL.
• In 1987 standardization => IEEE 1076-1987
• An improved version of the language was released in 1994 => IEEE standard1076-1993.
Dataflow VHDL Description:
• Circuit is described in terms of how data moves through the system.
• In the dataflow style you describe how information flows between registers in the system.
• The combinational logic is described at a relatively high level, the placement and operation of registers is specified quite precisely.
Behavioral VHDL Description:
• Circuit is described in terms of its operation over time.
• Representation might include, e.g., state diagrams, timing diagrams and algorithmic descriptions.
• The concept of time may be expressed precisely using delays (e.g., A <= B after 10 ns)
• If no actual delays is used, order of sequential operations is defined.
• In the lower levels of abstraction (e.g., RTL) synthesis tools ignore detailed timing specifications.
• The actual timing results depend on implementation technology and efficiency of synthesis tool.
FPGA ARCHITECTURE
FPGA Design Flow:
The ISE™ design flow comprises the following steps: design entry, design synthesis, design implementation, and Xilinx® device programming. Design verification, which includes both functional verification and timing verification, takes places at different points during the design flow.