16-08-2012, 10:11 AM
HDLC Controller Design
1HDLC Controller.pdf (Size: 1.25 MB / Downloads: 157)
Introduction
In this project we are to implement a high-level data link controller (HDLC) using verilog HDL. Layer two of the OSI model is the data link layer, and the most commonly used protocol is the HDLC protocol. The protocol provide reliable data link to the application by using zero-insertion and frame check sequence. Below is the basic frame structure.
8-bit Parallel to Serial Shift Register
Figure 1-2 shows the 8-bit Parallel to Serial Shift Register. When the control unit detects a new data, it asserts LOAD and the 8-bit register load the data into the register. After it loads the data, it shifts the content at every clock cycle and fill in a 0 into the MSB, and the output is connected to the FCS generator through S_DATA pin.
When the transmitter finishes transmitting a frame, or aborts a frame because the data is not valid, the control unit will not assert the LOAD signal. Because we fill in 0s into the MSB every time when we do the shift operation, the content of the registers will be reset to zero after translating every byte, thus no reset is needed when we reinitialize another transfer. The same argument applies to the FCS generation circuit as well.
Zero Detection
Figure 2-3 shows the Zero Detection circuit. When five consecutive 1s are received, the ZERO signal is asserted to notify the control unit that the coming data is an inserted zero. Control unit then gated the clock of FCS checker and serial-to-parallel unit to ensure correct output. The PASS signal is used to pass a 0 to the next stage during IDLE state.
16/32 bit FCS Checker
Figure 2-4 shows the FCS Checker unit. The unit consists of a 32-bit shift register, a 16-bit FCS generator and a 32-bit FCS generator. The data is shifted into the register from zero-detection stage, and the 16th bit is shifted into 16-bit FCS generator if FCS16_32 is 0. Otherwise the 32nd bit is shifted into 32-bit FCS generator.
If an inserted zero is detected in prior stage, the control unit gated the clock for one cycle and prevents the FCS data from corrupted.
The circuit compares the values of FCS generator and scan register every clock cycle and send the result to control unit through FCS_ERROR signal. The control unit has to sample the result at the right time to get the correct result.
Discussion
In this project, we learned how to start from the specification and build a design step by step. We chose to build the function blocks first because they are the easier part. However, we try to think ahead how those blocks might communicate with the control unit and choose the more flexible way to implement their function. After the function blocks are set, we start to build the state machine of the control unit. Sometimes we find that what we reserved in the function blocks are redundant and might need to remove them, and sometimes we need to add functions to both control unit and function blocks.
We designed two sets of transmitter and receivers, and we synthesized both of them. By comparing the result, we found that different coding style can affect the speed and area of a design. There are several ways to write a more concise code. For example, reduce the control signals and storage elements. By doing so, you get a simpler logic and less storage elements, which in turn enhance the speed and reduce the area.