30-09-2016, 09:31 AM
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INTRODUCTION
Image processing has been widly used in vision system, multimedia processor and consumer electronics.
Required:
Fast computation speed
Small Chip Size
Low Power consumptions
To improve Image Chip Performance 3D technology is used
Manufacturing Technologies of 3D-SICs
Die-to-Die
Built on multiple die, which are then aligned and bonded.
Thinning and TSV creation may be done before or after bonding.
Advantage of die-to-die is that each component die can be tested first, so that one bad die does not ruin an entire stack.
Die-to-Wafer
Built on two semiconductor wafers.
One wafer is diced; the singulated dice are aligned and bonded onto die sites of the second wafer.
Wafer-to-Wafer
Built on two or more semiconductor wafers, which are then aligned, bonded, and diced into 3D ICs.
Each wafer may be thinned before or after bonding.
Vertical connections are either built into the wafers before bonding or else created in the stack after bonding. These "through-silicon vias" (TSVs) pass through the silicon substrate(s) between active layers and/or between an active layer and an external bond pad.
Wafer-to-wafer bonding can reduce yields, since if any 1 of N chips in a 3D IC are defective, the entire 3D IC will be defective.
Benifites of 3D ICs
Footprint
Cost
Heterogeneous integration
Shorter interconnect
Power
Design
Circuit security
Bandwidth
3D LAYER ARCHTECTURE FOR PARALLEL IMAGE PROCESSING
CMOS IMAGE SENSOR LAYER
A/D CONVETER - transfer analog image signal to input digital image data.
Frame memory
Reconfigurable Memory
Process Element
Conclusion
A new reconfigurable system with RAM/ROM memory modules and 3D layer architecture is proposed for highly pipeline image processing chip.
Flexible data flow and direct system control can be realized by precise data fetch in RAM and ROM memory.
New 3D stacking layer architecture can also be applied to reduce image chip size and increase system pipeline speed.
Additional 3D network-on-chip connection system can satisfy 3D chip stacking requirements and enable global pipeline operation for multi-layer VLSI image system.
Further image robust methods, including self-repairable operation and re-healing system, are also used in proposed 3D image processing system.