09-02-2013, 02:49 PM
Fault Modeling
Fault Modeling.ppt (Size: 333.5 KB / Downloads: 201)
Why Model Faults?
I/O function tests inadequate for manufacturing (functionality versus component and interconnect testing)
Real defects (often mechanical) too numerous and often not analyzable
A fault model identifies targets for testing
A fault model makes analysis possible
Effectiveness measurable by experiments
Common Fault Models
Single stuck-at faults
Transistor open and short faults
Memory faults
PLA faults (stuck-at, cross-point, bridging)
Functional faults (processors)
Delay faults (transition, path)
Analog faults
For more details of fault models, see
M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000.
Fault Equivalence
Number of fault sites in a Boolean gate circuit is = #PI + #gates + # (fanout branches)
Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2.
If faults f1 and f2 are equivalent then the corresponding faulty functions are identical.
Fault collapsing: All single faults of a logic circuit can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset.
Fault Dominance
If all tests of some fault F1 detect another fault F2, then F2 is said to dominate F1.
Dominance fault collapsing: If fault F2 dominates F1, then F2 is removed from the fault list.
When dominance fault collapsing is used, it is sufficient to consider only the input faults of Boolean gates. See the next example.
In a tree circuit (without fanouts) PI faults form a dominance collapsed fault set.
If two faults dominate each other then they are equivalent.
Multiple Stuck-at Faults
A multiple stuck-at fault means that any set of lines is stuck-at some combination of (0,1) values.
The total number of single and multiple stuck-at faults in a circuit with k single fault sites is 3k – 1.
A single fault test can fail to detect the target fault if another fault is also present, however, such masking of one fault by another is rare.
Statistically, single fault tests cover a very large number of multiple faults.
Summary
Fault models are analyzable approximations of defects and are essential for a test methodology.
For digital logic single stuck-at fault model offers best advantage of tools and experience.
Many other faults (bridging, stuck-open and multiple stuck-at) are largely covered by stuck-at fault tests.
Stuck-short and delay faults and technology-dependent faults require special tests.
Memory and analog circuits need other specialized fault models and tests.