19-10-2012, 03:40 PM
The ARM Architecture
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Introduction
ARM is a a 32-bit RISC processor architecture currently being developed by
the ARM corporation. The business model behind ARM is based on licens-
ing the ARM architecture to companies that want to manufacture ARM-based
CPU’s or system-on-a-chip products. The two main types of licenses are the Im-
plementation license and the Architecture license. The Implementation license
provides complete information required to design and manufacture integrated
circuits containing an ARM processor core. ARM licenses two types of cores:
soft cores and hard cores. A hard core is optimised for a specific manufactur-
ing process, while a soft core can be used in any process but is less optimised.
The architecture license enables the licensee to develop their own processors
compliant with the ARM ISA.
History
The history of ARM started in 1983, when a company named Acorn Com-
puters was looking for a 16-bit microprocessor for their next desktop machine.
They quickly discovered that existing commercial microprocessors did not sat-
isfy their requirements. These processors were slower than standard memory
parts available at the time. They had complex instruction sets that included
instructions taking hundreds of cycles to execute, leading to high interrupt laten-
cies. The reason for these deficiencies was that early integrated microprocessors
were modelled after processors of minicomputers, which consisted of many chips,
were driven by microcode and had very complex instruction sets.
Therefore, Acorn engineers considered designing their own microprocessor.
However, resources required for such a project were well beyond what the com-
pany could afford. In early 80’s, microprocessor architectures became so com-
plex that it took many years even for large companies with significant expertise
in the area to design a new processor.
ARM ISA overview
In most respects, ARM is a RISC architecture. Like all RISC architectures, the
ARM ISA is a load-store one, that is, instructions that process data operate
only on registers and are separate from instructions that access memory. All
ARM instructions are 32-bit long and most of them have a regular three-operand
encoding. Finally, the ARM architecture features a large register file with 16
general-purpose registers. All of the above features facilitate pipelining of the
ARM architecture.
However, the desire to keep the architecture and its implementation as sim-
ple as possible prompted several design decisions that deviated from the original
RISC architecture. First, the original Berkeley RISC design used register win-
dows to speedup procedure invocations. ARM designers rejected this feature
as one that would increase size and complexity of the processor.
Registers
The ARM ISA provides 16 general-purpose registers in the user mode (see Fig-
ure 1). Register 15 is the program counter, but can be manipulated as a general-
purpose register. The general-purpose register number 14 has is used as a link
register by the branch-and-link instruction (see Section 3.4). Register 13 is typ-
ically used as stack pointer, although this is not mandated by the architecture.
The current program status register (CPSR) contains four 1-bit condition
flags (‘Negative’, ‘Zero’, ‘Carry’, and ‘oVerflow’) and four fields reflecting the
execution state of the processor. The ‘T’ field is used to switch between ARM
and Thumb (Section 8.1) instruction sets. The ‘I’ and ‘F’ flags enable normal
and fast interrupts respectively. Finally, the ‘mode’ field selects one of seven
execution modes: