07-05-2012, 01:00 PM
High-Level Synthesis-II
HighlevelSynthesis2.ppt (Size: 335.5 KB / Downloads: 28)
Architectural Synthesis
Constructing the macroscopic structure of a digital circuit starting from behavioural models that can be captured from Data flow or Sequencing Graph
Circuit Specification
Sequencing Graph
A set of functional resources, fully characterized in terms of area and execution delay
A set of constraints
Spatial Domain: Binding
A necessary condition for resource binding to produce a valid circuit implementation is that operation corresponding to the shared resource do not execute concurrently
A resource binding can be represented by a labeled hyper-graph, where the vertex set V represents operations and the edge set Eβ represents the binding of the operation to the resources