22-08-2012, 03:05 PM
High Resolution Application Specific Fault Diagnosis of FPGAs
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Abstract
High resolution diagnosis plays a critical role in silicon
debug and yield improvement. Application-dependent diagnosis
is also a key component in online testing and adaptive computing.
In this paper, a new technique for high resolution localization
of faults in the interconnects and logic blocks of an arbitrary
design implemented on a field-programmable gate array (FPGA)
is presented. This work is complementary to application-independent
detection methods for FPGAs. This technique can uniquely
identify any single bridging, open, or stuck-at fault in the interconnect
as well as any single functional fault, a fault resulting a
change in the truth table of a function, in the logic blocks. The
number of test configurations for interconnect diagnosis is logarithmic
to the size of the mapped design, whereas logic diagnosis is
performed in only one test configuration with less than 5% overhead
of built-in self diagnosis. These techniques have been further
extended for multiple fault diagnosis.
INTRODUCTION
SRAM-BASED field-programmable gate arrays (FPGAs)
are 2-D arrays of configurable logic blocks (CLBs) and
programmable switch matrices, surrounded by programmable
input/output blocks on the periphery. FPGAs are widely used in
many applications such as networking, storage systems, communication,
and adaptive computing, due to their reprogrammability,
flexibility, and reduced time-to-market.
The reprogrammability of FPGAs results in faster design and
debug cycle compared to application-specific integrated circuits
(ASICs). However, once the design is finalized and fixed, the
programmability becomes useless and costly if infield further
customization and reprogramability are not required. This is
why FPGAs are very costly for high volume fixed designs with
no further modifications compared to ASICs. Nevertheless, the
reconfigurability of FPGAs can be readily exploited for defect
tolerance at the manufacturing level as well as fault tolerance
for user applications.
PREVIOUS WORK
Test and diagnosis of FPGAs can be categorized into application-
independent and application-dependent methods. Application-
independent approaches target faults in the entire FPGA to
ensure functionality of the device for any possible user configurations.
In contrast, application-dependent techniques test and
diagnose the FPGA resources with respect to a particular application
mapped into the FPGA device.
Application-independent (manufacturing) testing of FPGAs
has been described in [1], [4], [11], [19], [24], [28], [31], [35].
Application-dependent testing of FPGAs has been addressed in
[2], [7], [22], [23] [32], [34] [36], [37].
Diagnosis of faults in FPGA logic blocks has been discussed
in [1], [13] [21], [29] [40]. Diagnosis of faults in the FPGA interconnects
has been addressed in [2], [8] [10], [12] [17], [18],
[27], [38], [43]. These techniques mainly fall within the category
of application-independent diagnosis. A survey of detection,
diagnosis, and fault tolerance techniques for FPGAs has
been presented in [3].
INTERCONNECT DIAGNOSIS
The interconnect resources in FPGAs can be categorized
as inter-CLB and intra-CLB resources. Inter-CLB routing
resources provide interconnections among CLBs. Inter-CLB
resources include programmable switch blocks and wiring
channels connecting switch blocks and CLBs. Intra-CLB resources
are located inside each CLB. Intra-CLB interconnects
include programmable multiplexers and wires inside CLBs.
Diagnosing faults in inter-CLB routing resources is addressed
in this section. For inter-CLB interconnect test and diagnosis,
the configuration of routing resources remains unchanged while
the configuration of logic resources is modified.
Results
Table II shows the number of test configurations required
for diagnosis of the ISCAS’89 sequential circuits mapped into
Xilinx Virtex FPGAs. Except for the last three (largest) circuits
which were mapped into XCV200, all other circuits were
mapped into the smallest device XCV50 in this FPGA family.
The second column shows the number of CLBs used for mapping
each circuit. The third column shows the number of faults
(pair-wise bridging faults, opens, and single stuck-at faults) in
the fault list. The last column shows the number of test configurations
for 100% diagnosis of single faults (stuck-at, opens, and
bridging faults).
SUMMARY AND CONCLUSION
In this paper, application-dependent diagnosis techniques for
faults in the interconnects and logic blocks of an arbitrary design
mapped into an FPGA are presented. For interconnect diagnosis,
multiple faults (open, stuck-at, or bridging fault) can
be uniquely identified. As shown in the paper, the number of
total test configurations for diagnosis of interconnects is logarithmic
to the size of the design. For logic block diagnosis,
a BISD approach is presented in which multiple faults can be
uniquely identified in only one test configuration.
This method can be used for defect tolerance by the manufacturer
in order to increase the manufacturing yield, i.e., as a
part of application-specific FPGA (ASFPGA) test flow, or in the
online self-repair schemes for fault tolerant applications.