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Abstract— This paper proposed a High speed FSM-based controller for programmable memory built-in selftest
for testing memory devices. This technique is popular because of its flexibility of new test algorithms. The
architecture of controller is designed to implement a new test algorithm has less number of operations and
this algorithm emphasis testing of high density memory ICs either faulty or good .The components of
controller is studied and designed using Verilog HDL. The analysis of the timing, logic area usage and speed
are presented.
INTRODUCTION
Memories are the most universal component today almost all system chips contain some type of embedded
memory, such as ROM, SRAM, DRAM, and flash memory. In the embedded domain, embedded RAMs of the
StrongArmSA110 occupy 90% of the total area. The projection is, by 2014, memory will represent more than
94% of the chip area in average SOC environment, according to the International Technology Roadmap for
Semiconductors 2007[7] the percentage of chip area occupied by memories in a design and the increasing trend
predicted for the next decade, with the advent of deep-submicron VLSI technology, the memory density and
capacity is growing but the clock frequency is never higher. The dominant use of embedded memory cores
along with emerging new architectures and technologies make providing a low area overhead and high speed
test solution for these on-chip memories a very challenging task.
Built- in self-test (BIST) [5] has been proven to be one of the most cost-effective and widely used solutions
for memory testing because the tests can run at circuit speed to yield a more realistic test time, no external test
equipment, reduced development efforts and on-chip test pattern generation to provide higher controllability and
observability.
There are several FSM-based controllers proposed in [1-10].In FSM-based memory BIST controller, counters
are the key component especially in FSM-based memory BIST controller but some FSM-based BIST controller
[2] excluded counter from its design. This type of architecture has optimum area overhead however less flexible
to allow any changes in the test algorithm. Usually, different counters [3], [4] are used to generate the address,
test data and read/write sequences. Two types of FSM-based BIST controller architectures are proposed in [5].
Both are designed by using a counter for the test pattern generator and test controller but one is using MISR
which is a part of the BIST controller block for output response analyzer (ORA) while another one is using
comparator which acts as an external block in the BIST system for ORA.
The FSM-based memory BIST has also progressed from non-programmable memory BIST to programmable
memory BIST. One of the early FSM-based P-MBISTs has two controllers; upper controller and lower
controller [6]. A two-dimensional circular buffer acts as the upper level controller which holds the necessary
parameters for the low level controller. The low level controller is the programmable FSM which is pre- programmed with instructions for read/write operation and addressing sequences for set of MARCH test
algorithms. This type of architecture has optimum area overhead however still less flexible to allow selection of
the test algorithms to be run on the memory cores.
Some of the latest MBIST [10] design combined both microcode-based and FSM based architecture to
compensate the area versus speed issue. A programmable MBIST merging FSM and Microcode Techniques [11]
using Macro Commands is designed by implementing clusters of microcode to control the read/write operation
and test data injection. This technique results in optimal lower area overhead compensate area and speed using
number of test algorithms.
The paper is organized as follows; section II introduces the proposed High Speed Programmable Memory
Built-In Self-Test controller (HP-MBIST) for MARCH C+. The experimental results are discussed in Section III
while Section IV concludes the paper.
II. MBIST CONTROLLER FOR MARCH C+
A. March C+ test algorithm
A test algorithm is a test procedure which uses a finite sequence of test elements for testing the memory
and identifying and locating defects [8].A test element contains a number of memory operations (access
commands), data pattern (background) specified for the read operation, address (sequence) specified for the read
and write operations. The test pattern used in the MARCH C+ Algorithm, It has less number of operations (14n)
where 14n is number of operation per memory word, due to less no of operations it requires less time to test the
memory under test (MUT) and Addressing order and their respective operation shown in Table 1 and fig 1
shown read-write operation in memory cells in ascending and descending addressing order respectively.
CONCLUSION
The simulation portrays that the tested data and the expected data are able to be compared in the architecture.
Hence it is concluded that this controller has the ability to detect faulty or good memory ICs. Synthesis result
shows that the FSM-based HP-MBIST controller employs only 76 instances with clock frequency 245.82 MHz
our design gives less usage of Logic Elements (LE) with High speed testing of memories as shown in above
Tables. It is justified that the FSM-based HP-MBIST controller consumes less area overhead and high speed
while the other design [9][10] consumes more area overhead and less speed the eexperimental results also shows
that the proposed BIST can be implemented with low area overhead.