21-01-2013, 01:16 PM
How to Transform an Architectural Synthesis Tool for Low Power VLSI Designs
1How to Transform.pdf (Size: 40.15 KB / Downloads: 21)
Abstract
High Level Synthesis (HLS) for Low Power VLSI design
is a complex optimization problem due to the
Area/Time/Power interdependence. As few low power
design tools are available, a new approach providing a
modular low power synthesis method is proposed.
Although based for the moment on a generic
architectural synthesis tool Gaut, the use of different
"commercial" tools is possible. The Gaut_w HLS tool is
constituted of low power modules : High level power
dissipation estimation, Assignment, Module selection
(operators and supply voltage), Optimization criteria
and Operators library. As illustration, power saving
factors on DWT algorithms are presented.
Introduction
Most VLSI researches have been focused on optimizing
circuit speed and area to perform complex signal
processing. Indeed, the rapid advance in VLSI
technology and the increasing computation required for
recent real time DSP applications infer large chips
density and high clock frequency. Then, the power
dissipation minimization in modern circuits, such as
mobile systems, is a crucial problem. To minimize the
power consumption of a system, VLSI researches work
on low power HLS tools. Power optimization can be
processed at several levels and the expecting power
saving factor at each level can be expressed as follows :
behavioral (10-100%), architectural (10-100%), logical
(10-50%) or physical (<20%) [3]. Therefore, at
behavioral and architectural levels, the expected saving
power is more significant : however these two domains
have been less explored in the literature. The method
integrated in our HLS Gaut_w proposes techniques in
order to optimize the design at these two levels.
Previous Works
Power estimation
There are three major sources of power dissipation in
digital CMOS circuits summarized in the following
equation (1). The first term represents the power
switching component, the second term is due to directpath
short circuit current and the last term is the power
dissipation due to leakage current.
Low power HLS tools
Few HLS optimization tools have been proposed in the
literature. Hyper_LP [6] has integrated high level
transformations and an ATP space exploration that
shows the supply voltage scaling impact on the design.
Concerning the module selection, most of previous
works only goals design area optimization [7].
Moreover, a module selection (different operator set at
different supply voltages) has been proposed which gives
the lower bounds on Area, Performance and Power
dissipation [8]. Scheduling methods have been presented
to schedule Multi-Voltage Datapaths [9].
HLS tool Gaut_w
The three entries are the algorithmic description of the
application (behavioral VHDL), the operator library and
the optimization criteria. At present, this tool is based on
the Gaut architectural synthesis tool [1,14], but such a
global method could be extended to any other tool.
Gaut_w contains two low power modules : Module
Selection that selects the best operator set and the best
supply voltage for a given time constraint, and
Assignment that assigns operations of the Data Flow
Graph (DFG) on physical operators in order to decrease
the transition rate of operator entries.
Formal library
The synchronous architecture synthesized by Gaut tool
used operators, memories, registers and a clock tree.
Operators :
Each operator has been simulated by the logic simulator
Compass to estimate the average power dissipation [10].
This estimate is the mean result of 5 simulations with
10.000 values length stimuli [11] implying a 95%
confidence interval and a less than 1% error. This
method provides a good trade-off between the simulation
time and precision of the results.
So, the library contains operators with different ATP
characteristics. For example, an addition function can be
realized with 4 different operators (Table I).
Memory library :
The great transistors number in a memory implies that
the power dissipation due to the leakage current is no
more negligible according to the switching component.
The power dissipation estimator integrated in the
Compass CAD tool is used to determine the switching
and the leakage component of the power dissipation.
These terms depend on the memory size.
Power dissipation estimation
The aim of this module is to give a fast power
dissipation estimation calculated at a high level of
abstraction. Currently, the method targets time
constrained DSP applications : operators used in the
circuit have an activation rate close to 100%.
The first estimation step is the scheduling probability
computation of each operation in the DFG [12]. This
allows to estimate the storage probability of each
variable (transfer via a register, the memory and a
register or transfer via a register) and then the probable
activity of the memory (Nmem) and the registers (NReg). The
probable register number can also be obtained allowing
to estimate the power dissipation of the clock tree. The
Ni operator activity is calculated on the DFG.
Conclusion
A generic method for low power VLSI design, integrated
in the Gaut_w HLS tool (Estimation and Optimization) is
presented here. This new approach is modular and is
realized before the architectural synthesis. Therefore, it
can be applied to any other architectural synthesis tool.
A fast power dissipation estimation at a high level of
abstraction has also been developed which compares
different time constrained DSP algorithms at an early
stage of the design.