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IEEE Standard VHDL Language Reference Manual
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Intent and scope of this standard
The intent of this standard is to define VHSIC Hardware Description Language (VHDL) accurately. Its
primary audiences are the implementor of tools supporting the language and the advanced user of the
language. Other users are encouraged to use commercially available books, tutorials, and classes to learn the
language in some detail prior to reading this standard. These resources generally focus on how to use the
language, rather than how a VHDL-compliant tool is required to behave.
At the time of its publication, this document was the authoritative definition of VHDL. From time to time, it
may become necessary to correct and/or clarify portions of this standard. Such corrections and clarifications
may be published in separate documents. Such documents modify this standard at the time of their publication
and remain in effect until superseded by subsequent documents or until the standard is officially revised.
Structure and terminology of this standard
This standard is organized into clauses, each of which focuses on some particular area of the language.
Every fifth line of each clause, not including clause headings, footers, and the clause title, is numbered in the
left margin. Within each clause, individual constructs or concepts are discussed in each subclause.
Each subclause describing a specific construct begins with an introductory paragraph. Next, the syntax of the
construct is described using one or more grammatical
productions
A set of paragraphs describing the meaning and restrictions of the construct in narrative form then follow.
Unlike many other IEEE standards, which use the verb
shall
to indicate mandatory requirements of the standard
and
may
to indicate optional features, the verb
is
is used uniformly throughout this document. In all
cases,
is
is to be interpreted as having mandatory weight.
Semantic description
The meaning and restrictions of a particular construct are described with a set of narrative rules immediately
following the syntactic productions. In these rules, an italicized term indicates the definition of that term and
identifiers appearing entirely in uppercase letters refer to definitions in package STANDARD (see 14.2).
Design entities and configurations
The
design entity
is the primary hardware abstraction in VHDL. It represents a portion of a hardware design
that has well-defined inputs and outputs and performs a well-defined function. A design entity may represent
an entire system, a subsystem, a board, a chip, a macro-cell, a logic gate, or any level of abstraction in
between. A
configuration
can be used to describe how design entities are put together to form a complete
design.
A design entity may be described in terms of a hierarchy of
blocks
, each of which represents a portion of the
whole design. The top-level block in such a hierarchy is the design entity itself; such a block is an
external
block that resides in a library and may be used as a component of other designs. Nested blocks in the hierarchy
are
internal
blocks, defined by block statements (see 9.1).
A design entity may also be described in terms of interconnected components. Each component of a design
entity may be bound to a lower-level design entity in order to define the structure or behavior of that
component. Successive decomposition of a design entity into components, and binding those components to
other design entities that may be decomposed in like manner, results in a hierarchy of design entities
representing a complete design. Such a collection of design entities is called a
design hierarchy
. The
bindings necessary to identify a design hierarchy can be specified in a configuration of the top-level entity in
the hierarchy.
This clause describes the way in which design entities and configurations are defined. A design entity is
defined by an
entity declaration
together with a corresponding
architecture body
. A configuration is defined
by a
configuration declaration
Entity declarations
An entity declaration defines the interface between a given design entity and the environment in which it is
used. It may also specify declarations and statements that are part of the design entity. A given entity
declaration may be shared by many design entities, each of which has a different architecture. Thus, an
entity declaration can potentially represent a class of design entities, each with the same interface.
Configuration declarations
The binding of component instances to design entities is performed by configuration specifications (see 5.2);
such specifications appear in the declarative part of the block in which the corresponding component
instances are created. In certain cases, however, it may be appropriate to leave unspecified the binding of
component instances in a given block and to defer such specification until later. A configuration declaration
provides the mechanism for specifying such deferred bindings.