10-02-2015, 11:02 PM
ABSTRACT
This paper presents Implementation of Mealy and Moore FSM based Serial Adder. Serial Adder is a circuit in which bits are added a pair at a time. When speed is not of great importance, it is a cost effective option to use a serial adder. Coding of design is done in Verilog HDL and the design is tested and simulated in ModelSim Simulator and is implemented on Xilinx Spartan3E 4 FPGA device.
In this project for simulation we use Modelsim6.4b for logical verification, and further synthesizing it on Xilinx ISE9.2i tool using target technology and performing placing & routing operation for system verification.
LANGUAGE USED:
Verilog HDL
TOOLS REQUIRED:
Modelsim 10.3b– Simulation
Xilinx ISE9.2i – Synthesize
project about vlsi and serial adder including.