25-02-2013, 11:58 AM
IMPROVISATION OF GABOR FILTER DESIGN USING VERILOG HDL
IMPROVISATION OF GABOR.pdf (Size: 355.24 KB / Downloads: 90)
Abstract
This paper presents the improvisation of
Gabor Filter design using Verilog HDL. This paper details
important enhancement made to the Digital Gabor filter
to minimize the sizing problem and the coding style that
synthesizable. The intention is to study, analyze, simplify
and improvise the design synthesis efficiency and accuracy
while maintaining the same functionality. The main
characteristic of the proposed approach was to replace the
parallel multiplication-accumulation unit (MAC) to a
serial multiplication-accumulation unit where the
convolution matrix takes place. This significant change
helps to reduce the sizing problem without jeopardizing
the functionality of the Digital Gabor Filter. The result
provides area efficiency architecture for the effective
design.
INTRODUCTION
ingerprint enhancement using Gabor filter is one of highly
computational complexity in fingerprint verification
process. Gabor filter has a complex valued convolution kernel
and a data format with complex values is used. So
implementing Gabor filter is very significant in fingerprint
verification process. Designing Gabor filter will help
enhancing the quality of fingerprint image. In fingerprint
recognition, Gabor filter optimally capture both local
orientation and frequency information from a fingerprint
image. By tuning a Gabor filter to specific frequency and
direction, the local frequency and orientation information can
be obtained. Thus, it is suited for extracting texture
information from images [1].
Digital Gabor Filter
Digital Gabor Filter was designed by transforming the design
into verilog using xilinx 10.1. The target device is Spartan 3A
family. The figure shown below is the summary of the
synthesized design. It can be seen that the utilization of the
resource of the device exceeded 100%[1]. This particular
point was where the improvement needed to be done to
achieve an effective and efficient design.
METHODOLOGY
The focus of this work is not to design a new digital Gabor
filter but to improve the design so it can be implemented on
the device. As an ASIC designer, there are three major factors
needed to be considered, maximization of speed,
minimization of area and power consumption. In this work,
minimization of area consumption will be the main priority.
RESULT AND DISCUSSION
After redesigning the gabor filter in verilog using Xilinx 10.1
software, the code was then synthesized. The summary of the
design was shown in figure 4. From the summary, the
numbers of warnings were reduced from 80 to 26 warnings.
The warnings generated are related to the incomplete if and
else statement which a latch might be generated. In this
summary, the target device Spartan3-S200 was used. This
device contains large resources suitable for a design such as
this. The numbers of Slices, Slice Flip Flops and LUTs were
significantly reduced.
Controller (CLU)
The control logic unit functions as controller for the data flow
in the filter. It gives instruction to the other blocks to do their
job. Basically, it gives the memory address to read data to the
MEMORY and give address of coefficient to the ALU.
This CLU will only generate the address location
when the ‘START’ signal is high. This signal indicats the
convolution process that has taken place but if the signal is
low, it indicates that the writing of image data into the
memory takes place.
CONCLUSION
The design enhancement proposed for Gabor Filter has
successfully reached. The area of the design has been
significantly reduced while the function of the filter is
perfectly maintained.
The numbers of slices used from previous design reduce
from 5759 slices to 1625 slices. This significant change is due
to the reduction of multiplier and adder used in the
multiplication and accumulation unit. The enhancement made
in the multiplication-accumulation unit has been proven
effectively reliable and functional.
By adjusting the memory and the controller unit, the
functionality of a complete and correct digital Gabor Filter is
obtained. Even though, the precision of this Gabor Filter is
0.001% away from the calculated data. By minimizing the
area, the speed of the design is relatively slower. It took 222
complete cycles to finish the convolution.