01-09-2014, 10:55 AM
This project presents a delay comparison of different multipliers for unsigned data, one uses a ripple carry, the second one uses a carry-look ahead adder, third one is carry skip adder,fourth one is carry select adder and the last one is pipelined parallel adder. The 8×8 Vedic multiplier module using Urdhva Tiryakbhyam Sutra uses four 4×4 Vedic multiplier modules, which is further based on 2x2 Vedic multiplier. Urdhva tiryakbhyam Sutra is most powerful Sutra, giving minimum delay for multiplication of all types of numbers, either small or large. Urdhva Triyagbhyam– Vedic method for multiplication which strikes a difference in the real process of multiplication itself. It causes parallel generation of intermediate products,removes unwanted multiplication steps with zeros and scaled to higher bit levels. The project’s main focus is on the speed/delay of the multiplication operation on 8-bit multipliers which are modeled using Verilog HDL, A hardware description language. The 8×8 Vedic multiplier is coded in Verilog, synthesized and simulated using Xilinx ISE 14.7 software. Th
This project presents a highly efficient method of multiplication – “Urdhva Tiryakbhyam Sutra” based on Vedic mathematics. It gives us method for hierarchical multiplier design and clearly indicates the computational advantages offered by Vedic methods. The computational path delay for proposed 8x8 bit Vedic multiplier is found to be 23.152 ns. Hence our motivation to reduce delay is finely fulfilled. Therefore, we observed that the Vedic multiplier is much more efficient than Array and Booth multiplier in terms of execution time (speed).