07-09-2016, 12:37 PM
Implementation of 4 bit array multiplier
using Verilog HDL and its testing on the
Spartan 2 FPGA
1453467367-MultiplierHDLFPGA.pdf (Size: 2.67 MB / Downloads: 24)
The aim here is to take you through the design and implementation steps of
FPGA implementation for 4-bit binary multiplier. The algorithm used here
is a simple one that uses repeated addition. Refer to HDL description for
Adder and Full Adder given in the text Digital Principles and Applications,
6e by Leach, Malvino and Saha, TMH, 2006.
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The gate level diagram of the 4 bit array multiplier was obtained as follows : -
(The unconnected inputs are the combinations of the input bits ANDed in pairs. The
exact combinations at each adder box can be found out from the Verilog code)