09-09-2014, 10:06 AM
Implementation of Adaptive Viterbi Decoder
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ABSTRACT
Viterbi algorithm is employed in wireless
communication to decode the convolutional codes;
those codes are used in every robust digital
communication systems. Such decoders are
complex & dissipiate large amount of power. Thus
the paper presents the design of an Adaptive
Viterbi Decoder (AVD) that uses survivor path
with parameters for wireless communication in an
attempt to reduce the power and cost and at the
same time increase in speed. Most of the researches
work to reduce power consumption, or work with
high frequency for using the decoder in the
modern applications such as 3 GPP, DVB, and
wireless communications. Field Programmable
Gate Array technology (FPGA) is considered a
highly configurable option for implementing many
sophisticated signal Processsing tasks. The
proposed decoder design is implemented on Xilinx
Spartan 3 , XC3S200 FPGA chip using VHDL
code and Xilinx ISE 9.1 used for synthesis.
INTRODUCTION
Most digital communication systems
nowadays convolutionally encoded the transmitted
data to compensate for Additive White Gaussian
Noise (AWGN), fading of the channel,
quantization distortions and other data degradation
effects. For its efficiency the Viterbi algorithm has
proven to be a very practical algorithm for forward
error correction of convolutionally encoded
messages. The requirements for the Viterbi decoder
or Viterbi detector depend on the applications used.
Most of the researches work to reduce cost, the
power consumption, or work with high frequency
for using the decoder in the modern applications
such as 3GPP, DVB, and Wireless
communications. Some of them comparing
between using FPGA, ASIC, and DSP to find
which one is suitable for the applications, other
studies the differences method for back trace unit
to find the correct path, and the other trying to
work with high frequency by using parallel
operations of decoder units
ARCHITECTURE OF VITERBI DECODER
The input to our proposed design is an
identified code symbols and frames, i.e. The design
decodes successive bit stream and the proposed
decoder has no need to segment the received bit
stream into n-bit blocks that are corresponding to a
stage in the trellis in order to compute the branch
metrics at any given point in time . The architecture
of the viterbi decoder is illustrated in fig 3.1.
Survivor Management Unit (SMU)
This is responsible for keeping track of the
information bits associated with the surviving paths
designated by the path metric Calculation. There
are two basic design approaches: Register
Exchange and Trace Back. In both techniques, a
shift register is associated with every trellis node
throughout the decoding operation . Since one of
the major interests is the low power design, the
proposed decoder has been implemented using the
trace back approach which dissipates less power.
The major disadvantage of the RE approach is that
its routing cost is very high especially in the case of
long-constraint lengths and it requires much more
resources.
MODIFIED ARCHITECTURE FOR ADAPTIVE VITERBI DECODER
The aim of the adaptive Viterbi Decoder
is to reduce the average computation and path
storage required by the Viterbi algorithm. Instead
of computing and retaining all 2K-1 possible paths,
only those paths which satisfy certain cost
conditions are retained for each received symbol at
each state node. Path retention is based on the
following criteria.
CONVOLUTIONAL CODES
The convolutional encoder is basically a
finite state machine. The k bit input is fed to the
constraint length K shift register and the n outputs
are calculated from the generator polynomials by
the modulo-2 addition. The generator polynomial
specifies the connections of the encoder to the
modulo-2 adder
CONCLUSION
• The processing execution time has been reduced
by removing the trace back algorithms that is used
to find the correct paths.
• The survivor path algorithm used, the address of
the memory unit to select the correct path which
specify the output code.Reconfigure the Viterbi decoder, and adaptive
Viterbi decoder units will give simple elements in
each unit and new algorithms.
• It was found that the survivor path decoder is
capable of supporting frequency up to 790 MHz for
constraint lengths 7, and 9 , rate 1/3 and long
survivor path is 4. The different constraint length
didn’t affect of the complexity of the decoder and
the processing time of computing the correct path.
•As mobile and wireless communication becomes
increasingly ubiquitous, the need for dynamic
reconfigure ability of hardware shall pose
fundamental challenges for communication
algorithm designers as well as hardware
architectures.
•This paper attempts to solve this problem for the
particular case of the Viterbi decoder, which is a
critical component at a physical layer of most
wireless communication systems.
•A new Viterbi decoder architectures have been
proposed. These results were evaluated and
assessed. Next the adopted design were coded in
VHDL and implemented on a SPARTAN 3.