20-04-2012, 03:37 PM
Implementation of Multi-Valued Logic Gates Using Full Current-Mode CMOS Circuits
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Introduction
Multi-valued logic, MVL, is a hybrid design technique
of binary logic and analogue signal processing which
retains noise advantages of a digital signal while processing
greater informational content in analogue manner.
MVL has also the advantages of less interconnection,
and circuitry to effectively implement many
arithmetic and logical functions on one chip [1–3].
Due to design simplicity and larger dynamic range,
current-mode approach is preferred for designingMVL
circuits. Some current-mode multi-valued logic (CMMVL),
studies are proposed for I2L [4, 5], for CCD [6],
and for CMOS [1, 7]. Most CMOS CM-MVL studies
prefer using voltage-mode internal circuits for switching
a desired level of output current by exploiting the
comparator scheme in [8].
Analog Design Constraints on Operating Radix
Linear current range described in the previous section is
not the only parameter for choosing the operating radix.
The step size between logic levels, which is limited by
the noise margin, must also be considered.
The output current of the mirror circuit in Fig. 17
is constituted with random and nominal components.
The former is attributed to random design parameter
variations, and physical noise current generated in the
devices [20, 21].
Conclusions
In this study we introduced a complete set of multivalued
logic gates and a novel current-mode threshold
circuit. Based on this circuit, MVL literal and cyclic
gates are constructed. Designs are technology independent,
hence allowing different technology realizations
in the same simplicity. As an application, a radix-8
full-adder circuit is designed with a cyclic gate. The
full-adder circuit exhibits faster dynamic behavior with
much less chip area compared to its binary counterparts.
The disadvantages of current mode multi-valued
logic circuits are the larger static power dissipation
and reduced noise margins for high radices.