09-02-2013, 11:01 AM
Implementation of Non-Pipelined and Pipelined Data Encryption Standard (DES) Using Xilinx Virtex-6 FPGA Technology
1Implementation of Non-Pipelined .pdf (Size: 411.91 KB / Downloads: 18)
Abstract
Data encryption process can easily be quite
complicated and usually requires significant computation
time and power despite significant simplifications. This paper
discusses about pipelined and non-pipelined implementation of
one of the most commonly used symmetric encryption algorithm,
Data Encryption Standard (DES). The platform used for this
matter is, Xilinx new high performance silicon foundation,
Virtex-6 Field Programmable Gate Array technology. Finite state
machine is used only in non-pipelined implementation, and it is
not implemented for the pipelined approach. The testing of the
implemented design shows that it is possible to generate data in
16 clock cycles when non-pipelined approach is employed. When
pipelined approach is employed on the other hand, 17 clock
signals are required for the initial phase only, and one clock
signal is sufficient afterwards for each data generation cycle. The
Very High Speed Integrated Circuit Hardware Description
Language (VHDL) is used to program the design.
INTRODUCTION
The most commonly used technique for producing
confidentiality in data transmission is symmetric encryption
[3], [11]. Symmetric encryption scheme, also referred to as
single key encryption method, has five main modules [11].
The term plaintext is used to denote the original incoming
data. The key is an essential part of the encryption process and
it provides the secure data traffic among the sender and the
recipient. Encryption algorithm performs various
mathematical and logical functions on the plaintext by using
the key. Cipher data is the encrypted message produced by
encryption algorithm by using the key and the plain text.
DES ALGORITHM
DES algorithm uses complicated logical functions such as
various types of permutations, XOR and SHIFT functions.
Since the key employed is transformed to mentioned function,
by following the algorithm provided, the only way to decrypt
the plaintext is to apply the same key in decryption algorithm
as well. DES takes 64 bits plaintext and 56 bits key as input
and generates 64 bits cipher data as output [2]. The block
diagram of algorithm is shown in Fig. 1. Sometimes the key is
considered as 64 bits where 8 bits is used for parity check. The
DES structure is first described by Horst Feistel in 1973 [2], as
shown in Fig. 2.
In this method, after initial permutation (IP) of the plaintext,
it is divided into two halves L(0), R(0). The two halves pass
through 16 rounds. Then after the final permutation (FP), the
cipher data is produced. IP and FP work exactly in opposite
ways to each other [2].
XILINX VIRTEX-6 FPGA
An FPGA is an integrated circuit which contains array of
programmable logic cell in rows and columns [5]. FPGAs’
performance and features vary for different vendors. The
Virtex-6 is a new FPGA from Xilinx built on 40nm process
technology [15] which is one of the fastest FPGA in the world.
The Virtex-6 family aims to provide up to 50% lower power
and 20% lower cost than previous generation.
The basic programmable part of FPGA is called slice. Each
Virtex-6 FPGA slice contains four LUTs (Look up Table) and
eight flip-flops. Some of the slices can use their LUTs as
distributed RAM [15]. The simplified diagram of the slice is
shown in Fig. 5. The FPGA model used in this paper is
xc6vlx240t-3ff1156. The product features are shown in Table
I [15].
CONCLUSION
Non-pipelined and fully pipelined DES algorithm
implementations are presented in this paper. The results show
that is possible to implement a design by using FSM in order
to operate at high system clock frequency (1.2 GHz).
Similar to the studies presented in [10], [1], [12], [7], the
original implementation of the DES algorithm is considered
and the theoretical part is not modified. The implementation
presented by using Virtex-6 family FPGAs have better
performance than the existing ones since it is possible to have
throughput going up to18.82 Gbps by implementing a fully
pipelined design including pipelined key schedulers.
It is desirable to implement the improved DES algorithm
presented in [3] by using a similar approach in order to test the
performance improvements for the future studies.