09-11-2012, 05:28 PM
I am Mathew George mtech student in vlsi and embedded systems , i need the ppt and seminar report of topic Improved Design of High-Performance Parallel Decimal Multipliers .This topic i have searched lot no detail was available so can u add details
Abstract—The new generation of high-performance decimal floating-point units (DFUs) is demanding efficient implementations of parallel decimal multipliers. In this paper, we describe the architectures of two parallel decimal multipliers. The parallel generation of
partial products is performed using signed-digit radix-10 or radix-5 recodings of the multiplier and a simplified set of multiplicand
multiples. The reduction of partial products is implemented in a tree structure based on a decimal multioperand carry-save addition
algorithm that uses unconventional (non BCD) decimal-coded number systems. We further detail these techniques and present the
new improvements to reduce the latency of the previous designs, which include: optimized digit recoders for the generation of 2n-tuples
(and 5-tuples), decimal carry-save adders (CSAs) combining different decimal-coded operands, and carry-free adders implemented by
special designed bit counters. Moreover, we detail a design methodology that combines all these techniques to obtain efficient
reduction trees with different area and delay trade-offs for any number of partial products generated. Evaluation results for 16-digit
operands show that the proposed architectures have interesting area-delay figures compared to conventional Booth radix-4 and
radix-8 parallel binary multipliers and outperform the figures of previous alternatives for decimal multiplication