13-06-2013, 02:48 PM
Integrated Energy-Harvesting Photodiodes With Diffractive Storage Capacitance
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Abstract
Integrating energy-harvesting photodiodes with
logic and exploiting on-die interconnect capacitance for energy
storage can enable new, ultraminiaturized wireless systems.
Unlike CMOS imager pixels, the proposed photodiode designs
utilize p-diffusion fingers and are implemented in a conventional
logic process. Also unlike specialized solar cell processes, the
designs utilize the on-chip metal interconnect to form a diffraction
grating above the p-diffusion fingers which also provides
capacitive energy storage. To explore the tradeoffs between optical
efficiency and energy storage for integrated photodiodes, an
array of photovoltaics with various diffractive storage capacitors
was designed in a 90-nm CMOS logic process. The diffractive
effects can be exploited to increase the photodiodes’ response
to off-axis illumination. Transient effects from interfacing the
photodiodes with switched-capacitor DC–DC converters were
examined, with measurements indicating a 50% reduction in the
output voltage ripple due to the diffractive storage capacitance.
INTRODUCTION
CMOS technology scaling has continued to reduce the
size and active power consumption of electronic devices.
This trend has opened the door for energy harvesters to power
wireless systems through extracting mechanical, thermal, or
solar energy from the environment. Increased system integration
has allowed solar energy harvesters, in the form of
passive photodiodes, to be implemented on the same silicon
die as active circuitry, which can be powered by the harvested
energy. These integrated photodiodes [1], [2] are modeled
after a passive pixel architecture [3], which can form the
basis for CMOS imagers. Previous works have outlined the
use of environmental energy-harvesting for powering wireless
systems [4]–[23]. For many wireless systems, photovoltaics
(PVs) are a viable source for energy-harvesting [5]–[16].
Integrating the solar energy-harvesting on the same die as
other parts of the system enables reduced system cost and
size.
INTEGRATED PHOTODIODE DESIGN
Fig. 2(a) shows the layout for an integrated photodiode.
A 2-D photodiode structure, consisting of p-diffusion fingers
implanted in an n-well, was implemented. Vertical parallel
plate storage capacitance using metal routing layers can be
constructed on top of the fingers, forming an optical diffraction
grating [2]. Metal density design rules are becoming
stricter as technology continues to scale in modern CMOS
processes. Using metal interconnect as storage capacitance can
help satisfy these density constraints while providing useful
functionality. Since the spacing between these vertical metal
strips doubles as the aperture for the incident light, the storage
capacitance will have an optical filtering effect. To increase
the optical efficiency in order for the photodiode to harvest
additional energy from off-axis illumination (large incident
angle, φi ) a periodic grating sequence can be implemented
by varying the height of the metal fingers. Fig. 2(b) shows a
die photo of the fabricated photodiode test structures.
EXPERIMENTAL RESULTS
In total, six different geometries (D1–D6) for the diffractive
storage capacitance were designed and tested. Each diode
occupied the same area and had the same diffusion layout in
Fig. 2(a), but incorporated a different metal diffraction grating
using interconnect layers metal 1 through metal 6 (M1–M6).
A goal of this paper is to determine the impact the metal storage
capacitance has on the photodiodes’ optical efficiency. The
first diode D1 is the control, where only M1 was used to connect
the p-diffusion fingers together. Diodes D2 and D3 used
M1 through M6, and were based on quadratic residue sequence
diffusers with periods 5 and 7, respectively. Diodes D4 and D5
also used M1 through M6, but were based on a primitive root
sequence with periods 4 and 6, respectively. Diode D6 was
also a control, where its diffraction grating occupied all six
layers throughout for a maximum metal fill density.
PHOTODIODE MODELING
An equivalent circuit model for an idealized PV cell consists
of a current source in parallel with an ideal diode. The PV cell
is irradiated by solar energy which generates free carriers (and
current) and is represented by the current source. To model
the nonlinear I−V characteristics of a PV cell, diode D1 is
introduced. The current in the PV cell is constant under the
assumption that the irradiance and temperature are constant.
However, this simple model is insufficient in practice
because it neglects the nonidealities of fabricated PV cells.
Fig. 12 shows a more accurate model of the PV cell with the
ideal current source replaced by a voltage-controlled current
source (VCCS) and the addition of a second diode.
CONCLUSION
This paper has been compared to recent works in Table V.
Similar to [1], Ferri et al. measured analogous parameters such
as efficiency; however, at a lower light intensity, and therefore
lower and possibly scaled Voc and Isc. They also point out
that connecting the p-substrate to the p-diffusions, like in this
paper, allows the beneficial use of the parasitic diode formed
between the substrate and the n-well, but does not allow
for integration with the active circuitry [8]. By measuring
both the p-diffusion/n-well and the p-sub/n-well photodiodes
separately, it is concluded that the photogenerated current, or
Isc, is four times smaller for the floating p-diffusion/n-well
photodiode than the two in parallel. Ay utilized the p+/n-well
photodiode to harvest energy while shorting the p-sub/n-well
photodiode, both of which make up an active pixel sensor of a
54 × 50 array [9]. Similar systems of energy-harvesting image
sensors have been proposed [10]–[12].