21-12-2012, 06:16 PM
Integrated Microchannel Cooling for Three-Dimensional Electronic Circuit Architectures
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ABSTRACT
The semiconductor community is developing three-dimensional circuits that integrate
logic, memory, optoelectronic and radio-frequency devices, and microelectromechanical
systems. These three-dimensional (3D) circuits pose important challenges for thermal
management due to the increasing heat load per unit surface area. This paper theoretically
studies 3D circuit cooling by means of an integrated microchannel network. Predictions
are based on thermal models solving one-dimensional conservation equations for
boiling convection along microchannels, and are consistent with past data obtained from
straight channels. The model is combined within a thermal resistance network to predict
temperature distributions in logic and memory. The calculations indicate that a layer of
integrated microchannel cooling can remove heat densities up to 135 W/cm2 within a 3D
architecture with a maximum circuit temperature of 85°C. The cooling strategy described
in this paper will enable 3D circuits to include greater numbers of active levels while
exposing external surface area for functional signal transmission.
Introduction
Three-dimensional ~3D! circuit architectures enable the integration
of logic with memory, RF devices, optoelectronic devices,
and microelectromechanical systems on a single chip. These 3D
circuits offer reduced communication delay between modules
~e.g., between logic and memory!, reduced interconnect length,
and even improved reliability @1,2#. However, 3D circuits pose
thermal management challenges due to the significant increase in
total power generated per unit available surface area for cooling.
Furthermore, the power generated per unit volume within a 3D
circuit can vary significantly, yielding large junction temperature
nonuniformities that can impair the collective operation of the
circuit @2#. Another problem is that the increased functionality of
the circuit demands greater surface area for input and output of
electrical, optical, RF, and other types of signals, which further
reduces the surface area available for heat removal. While the
semiconductor research community is actively studying the electrical
performance and manufacturing methods of 3D circuits with
as many as one hundred device layers @3#, the introduction of a
new cooling approach is a critical issue in its implementation.
Three-Dimensional Circuit Fabrication Methods
Although this study focuses on the theoretical potential of microchannel
cooling for enabling 3D circuits, a much larger challenge
will be integrating the process steps for the microfluidic
channels within the already demanding process flow required to
make 3D circuits. The main goal of 3D circuit processing is creating
additional semiconducting layers of silicon, germanium, gallium
arsenide, or other materials on top of an existing device layer
on a semiconducting substrate. There are several possible fabrication
technologies to form these layers. The most promising nearterm
techniques are wafer bonding @14–17#, silicon epitaxial
growth @18–20#, and recrystallization of polysilicon @21–24#. Figure
3 shows a schematic of 3D circuits illustrating two different
fabrication schemes. The choice of a particular technology will
depend on the requirements of the integrated circuit system,
manufacturability, and process compatibility with current technology.
Previous Research on Two-Dimensional Microchannel
Heat Sinks
There has been much past research on microchannel cooling in
two-dimensional ~2D! heat sinks, which forms the groundwork for
the modeling study performed in the current study on a 3D microchannel
network. Since Tuckerman and Pease @29# demonstrated
that single-phase microchannel cooling can remove
790 W/cm2, much of the subsequent research has focused on the
physics and optimization of two-phase flow in microchannels.
Perhaps the closest previous work to the current integrated 3D
microchannel network is that of Wei and Joshi @30#, who proposed
stacked microchannels for cooling of microelectronic devices. A
number of parallel microchannels are fabricated in the surface of a
substrate and then each layer is bonded into a stacked heat sink
which is attached to the chip. They proposed a simple thermal
resistance network model and performed optimization to minimize
the overall thermal resistance.
Past work indicates that the two-phase flow in microchannels
exhibits different flow regimes and heat transfer characteristics
compared to macroscale convective boiling @31#. Experimental
investigation on boiling flow transition in microchannels showed
no bubble generation in channels with hydraulic diameters ranging
from 150 to 650 mm, although the heat transfer rate suggested
that phase change occurred @32,33#.
Modeling
Figure 4 shows a schematic of the microchannels implemented
in a 3D circuit architecture within a coordinate system. It is assumed
that the microchannels are distributed uniformly and fluid
flows through each channel with the same liquid flow rate. The
working fluid, water, flows in the z direction with a mass flow rate
of m˙ . The junction heat generation rate q9 is assumed to vary only
in the z direction. Using symmetry, a one-dimensional conjugate
conduction/convection heat transfer analysis is applied to only one
channel for each layer.
Results and Discussion
Analysis is performed to simulate 3D IC cooling performance
with microchannels fabricated between two silicon layers using
deep reactive ion etching and wafer bonding techniques @15,17#.
Figure 7 illustrates four different 3D stack schemes for a given
flow direction. To simulate nonuniform power distributions in
practical 3D ICs, the device is divided into logic circuitry and
memory, where 90% of the total power is dissipated from the
logic and 10% from the memory @53#. This work assumes that the
heat generation represents the power dissipation from the junctions
and also from interconnect Joule heating. For case ~a!, the
logic circuit occupies the whole device layer 1, while the memory
is on the device layer 2. In the other cases, each layer is equally
divided into memory and logic circuitry. For case ~b!, a high heat
generation area is located near the inlet of the channels, while it is
near the exit of channels for case ~c!. Case ~d! has a combined
thermal condition in which layer 1 has high heat flux and layer 2
has low heat dissipation near the inlet. The total circuit area is
4 cm2, while the total power generation is 150 W.